SY100E155JZTR

更新时间： 2024-01-21 22:05:06

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	67K
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数据手册

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SY100E155JZTR 数据手册

SY10E155

SY100E155

FINAL

6-BIT 2:1

MUX-LATCH

FEATURES

DESCRIPTION

■ 750ps max. LEN to output

■ Extended 100E VEE range of –4.2V to –5.5V

■ 700ps max. D to output

The SY10/100E155 offer six 2:1 multiplexers followed

by latches with single-ended outputs, designed for use in

new, high-performance ECL systems. The two external

latch-enable signals (LEN1 and LEN2) are gated through a

logical OR operation before use as control for the six

latches. When both LEN1 and LEN2 are at a logic LOW, the

latches are transparent, thus presenting the data from the

multiplexers at the output pins. If either LEN1 or LEN2 (or

both) are at a logic HIGH, the outputs are latched.

ThemultiplexeroperationiscontrolledbytheSEL(Select)

signal which selects one of the two bits of input data at each

mux to be passed through.

■ Single-ended outputs

■ Asynchronous Master Reset

■ Dual latch-enables

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E155

■ Available in 28-pin PLCC package

The MR (Master Reset) signal operates asynchronously

to take all outputs to a logic LOW.

BLOCK DIAGRAM

PIN CONFIGURATION

MUX

SEL

25 24 23 22 21 20 19

MUX

SEL

LEN

VCC

PLCC

TOP VIEW

J28-1

VEE

SEL

VCCO

MUX

SEL

10 11

MUX

SEL

MUX

SEL

PIN NAMES

D0a–D5a

D0b–D5b

SEL

Function

Input Data a

Input Data b

MUX

SEL

D5b

Data Select Input

Latch Enables

Master Reset

Outputs

SEL

LEN1, LEN2

LEN

Q0–Q5

VCCO

VCC to Output

Rev.: C

Amendment: /1

Issue Date: February, 1998

12 3 4

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