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SY100E155JZ-TR PDF预览

SY100E155JZ-TR

更新时间: 2024-11-23 13:14:11
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麦瑞 - MICREL /
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4页 67K
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SY100E155JZ-TR 数据手册

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SY10E155  
SY100E155  
FINAL  
6-BIT 2:1  
MUX-LATCH  
FEATURES  
DESCRIPTION  
750ps max. LEN to output  
Extended 100E VEE range of –4.2V to –5.5V  
700ps max. D to output  
The SY10/100E155 offer six 2:1 multiplexers followed  
by latches with single-ended outputs, designed for use in  
new, high-performance ECL systems. The two external  
latch-enable signals (LEN1 and LEN2) are gated through a  
logical OR operation before use as control for the six  
latches. When both LEN1 and LEN2 are at a logic LOW, the  
latches are transparent, thus presenting the data from the  
multiplexers at the output pins. If either LEN1 or LEN2 (or  
both) are at a logic HIGH, the outputs are latched.  
ThemultiplexeroperationiscontrolledbytheSEL(Select)  
signal which selects one of the two bits of input data at each  
mux to be passed through.  
Single-ended outputs  
Asynchronous Master Reset  
Dual latch-enables  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E155  
Available in 28-pin PLCC package  
The MR (Master Reset) signal operates asynchronously  
to take all outputs to a logic LOW.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
D
0a  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q
Q
Q
Q
Q
Q
D
MUX  
SEL  
E
N
D
0b  
1a  
R
R
R
R
R
R
25 24 23 22 21 20 19  
D
5b  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q5  
D
D
MUX  
SEL  
LEN  
1
Q
4
E
N
LEN  
2
VCC  
D
1b  
2a  
PLCC  
TOP VIEW  
J28-1  
VEE  
Q
Q
3
2
MR  
2
D
D
SEL  
VCCO  
3
MUX  
SEL  
E
N
D
0b  
4
Q1  
D
2b  
3a  
5
6
7
8
9
10 11  
D
D
MUX  
SEL  
E
N
D
3b  
4a  
D
D
MUX  
SEL  
PIN NAMES  
E
N
D
4b  
5a  
Pin  
D0a–D5a  
D0b–D5b  
SEL  
Function  
D
D
Input Data a  
Input Data b  
MUX  
SEL  
E
N
D5b  
Data Select Input  
Latch Enables  
Master Reset  
Outputs  
SEL  
LEN1, LEN2  
MR  
LEN  
1
LEN  
2
Q0–Q5  
VCCO  
MR  
VCC to Output  
Rev.: C  
Amendment: /1  
Issue Date: February, 1998  
1

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