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SY100E163JC PDF预览

SY100E163JC

更新时间: 2024-11-19 22:34:47
品牌 Logo 应用领域
麦瑞 - MICREL 复用器
页数 文件大小 规格书
4页 62K
描述
2-BIT 8:1 MULTIPLEXER

SY100E163JC 数据手册

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2-BIT 8:1  
MULTIPLEXER  
SY10E163  
SY100E163  
FEATURES  
DESCRIPTION  
850ps max. propagation delay  
Extended 100E VEE range of –4.2V to –5.5V  
Differential outputs  
The SY10/100E163 offer two 8:1 multiplexers designed  
for use in new, high-performance ECL systems. The E163  
has differential outputs and common select inputs. The  
select inputs (SEL0, SEL1, SEL2) determine which one of  
the eight data inputs (A0–A7, B0–B7) is propagated to the  
output.  
Internal 75Kinput pulldown resistors  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Fully compatible with Motorola MC10E/100E163  
Available in 28-pin PLCC package  
PIN CONFIGURATION  
BLOCK DIAGRAM  
A0  
A1  
A2  
25 24 23 22 21 20 19  
B
1
A
3
4
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
QB  
QB  
QA  
QA  
B0  
SEL  
0
VCC  
A
PLCC  
TOP VIEW  
J28-1  
VEE  
NC  
A5  
SEL  
1
2
VCCO  
SEL  
2
0
3
QA  
QA  
A
6
7
A
4
A
5
6
7
8
9
10 11  
SEL  
SEL  
0
1
SEL  
2
TO SIDE B  
PIN NAMES  
Pin  
Function  
A0–A7  
A Data Inputs (D)  
B Data Inputs (D)  
Select Inputs  
B0–B7  
SEL0, 1, 2  
QA, QB  
QA, QB  
VCCO  
True Outputs  
Inverting Outputs  
VCC to Output  
Rev.: C  
Amendment: /1  
Issue Date: February, 1998  
1

SY100E163JC 替代型号

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MC100E457FNG ONSEMI

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