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SY100E175JCTR PDF预览

SY100E175JCTR

更新时间: 2024-10-01 20:21:23
品牌 Logo 应用领域
美国微芯 - MICROCHIP 逻辑集成电路触发器
页数 文件大小 规格书
4页 182K
描述
D Latch, 100E Series, 1-Func, Low Level Triggered, 9-Bit, True Output, ECL, PQCC28, PLASTIC, LCC-28

SY100E175JCTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.81
其他特性:WITH PARITY GENERATION系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.48 mm逻辑集成电路类型:D LATCH
湿度敏感等级:1位数:9
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:-4.5 V
最大电源电流(ICC):132 mAProp。Delay @ Nom-Sup:0.8 ns
传播延迟(tpd):0.9 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:LOW LEVEL宽度:11.48 mm
Base Number Matches:1

SY100E175JCTR 数据手册

 浏览型号SY100E175JCTR的Datasheet PDF文件第2页浏览型号SY100E175JCTR的Datasheet PDF文件第3页浏览型号SY100E175JCTR的Datasheet PDF文件第4页 
5  
SY10E175  
9-BIT LATCH  
WITH PARITY  
SY100E175  
FEATURES  
DESCRIPTION  
9-bit latch  
The SY10/100E175 are 9-bit latches. They also feature  
a tenth latched output (ODDPAR) which is formed as the  
odd parity of the nine data inputs (ODDPAR is HIGH if  
an odd number of the inputs are HIGH).  
The E175 can also be used to generate byte parity by  
using D8 as the parity-type select (L = even parity, H =  
odd parity) and using ODDPAR as the byte parity output.  
The LEN pin latches the data when asserted with a  
logical high and makes the latch transparent when placed  
at a logic low level.  
Extended 100E VEE range of –4.2V to –5.5V  
Parity detection/generation  
800ps max. D to Output  
Reset  
Internal 75Kinput pull-down resistors  
Fully compatible with Motorola MC10E/100E175  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
D0 – D8  
LEN  
Function  
D0  
D
Q
Q0  
Data Inputs  
EN  
Latch Enable  
Master Reset  
Data Outputs  
Parity Output  
VCC to Output  
R
MR  
Q0 – Q8  
ODDPAR  
VCCO  
bits  
1 7  
D8  
D
Q
Q8  
EN  
R
D
Q
ODDPAR  
EN  
R
LEN  
MR  
Rev.: F  
Amendment:/0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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