SY100E193JCTR

更新时间： 2024-11-19 22:25:27

品牌	Logo	应用领域
麦瑞 - MICREL		逻辑集成电路
页数	文件大小	规格书
4页	66K
描述
ERROR DETECTION/ CORRECTION CIRCUIT

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SY100E193JCTR 数据手册

ERROR DETECTION/

CORRECTION CIRCUIT

SY10E193

SY100E193

FEATURES

DESCRIPTION

■ Hamming code generation

■ Extended 100E VEE range of –4.2V to –5.5V

■ 8-bit wide

The SY10/100E193 are error detection and correction

(EDAC) circuits designed for use in new, high- performance

ECL systems. The E193 generates hamming parity codes

on an 8-bit word as shown in the block diagram. The P5

output gives the parity of the whole word. PGEN provides

word parity after Odd/Even parity control and gating with

the BPAR input. PGEN also feeds into a 1-bit shiftable

The combinatorial part of the device generates the same

code pattern as the Motorola MC10193.

Used in conjunction with 12-bit parity generators, such

as the E160, a SECDED (single error correction, double

error detection) error system can be designed for a multiple

of an 8-bit word.

■ Expandable for more width

■ Provides parity register

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E193

■ Available in 28-pin PLCC package

PIN CONFIGURATION

PIN NAMES

Function

Check Bit Inputs

B0–B7

BPAR

EV/OD

Check Bit Parity Input

Even/Odd Parity Select

Parity Enable

25 24 23 22 21 20 19

EV/OD

BPAR

PARERR

HOLD

S-IN

Syndrome Hold Input

Syndrome Bit Input

Syndrome Bit Shift

Clock Input

TOP VIEW

PLCC

J28-1

SHIFT

CLK

CCO

P1–P5

PGEN

Parity Output

10 11

Parity Generate Output

Parity Error Output

VCC to Output

PARERR/PARERR

VCCO

Rev.: C

Amendment: /1

Issue Date: February, 1998

12 3 4

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