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SY100E212 PDF预览

SY100E212

更新时间: 2024-11-20 05:04:31
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 64K
描述
3-BIT SCANNABLE REGISTER

SY100E212 数据手册

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2  
3-BIT SCANNABLE  
REGISTER  
SY10E212  
SY100E212  
DESCRIPTION  
FEATURES  
Scannable version E112 driver  
Extended 100E VEE range of –4.2V to –5.5V  
1025ps max. CLK to Output  
Dual differential outputs  
The SY10/100E212 are scannable registered ECL  
drivers typically used as fan-out memory address drivers  
for ECL cache driving. In a VLSI array-based CPU design,  
use of the E212 allows the user to conserve array output  
cell functionality and also output pins.  
Master Reset  
The input shift register is designed with control logic  
which greatly facilitates its use in boundary scan  
applications.  
Internal 75Kinput pull-down resistors  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Fully compatible with Motorola MC10E/100E212  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
S-OUT  
Pin  
D0 – D2  
Function  
Data Inputs  
Scan Input  
Q
2b  
2a  
D
D
D
Q
S-IN  
Q
Q
Q
Q
Q
2a  
2b  
D2  
D1  
D0  
LOAD  
LOAD/HOLD Control  
Scan Control  
Clock  
SHIFT  
CLK  
Q
Q
1b  
1a  
MR  
Master Reset  
Scan Output  
True Outputs  
Inverting Outputs  
VCC to Output  
S-OUT  
Q
Q
1a  
1b  
Q[0:2]a, Q[0:2]b  
Q[0:2]a, Q[0:2]b  
VCCO  
Q
Q
0b  
0a  
Q
Q
0a  
0b  
S-IN  
LOAD  
SHIFT  
CLK  
MR  
Rev.: F  
Amendment:/0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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