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SY100E212JC PDF预览

SY100E212JC

更新时间: 2024-11-19 22:42:35
品牌 Logo 应用领域
麦瑞 - MICREL 触发器逻辑集成电路输入元件
页数 文件大小 规格书
4页 65K
描述
3-BIT SCANNABLE REGISTER

SY100E212JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.35
其他特性:DIAGNOSTIC SCAN REGISTER WITH SELECTABLE SERIAL AND PARALLEL DATA INPUT系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.48 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:1位数:3
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):240
电源:-4.5 V传播延迟(tpd):1.025 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Other Logic ICs表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:11.48 mmBase Number Matches:1

SY100E212JC 数据手册

 浏览型号SY100E212JC的Datasheet PDF文件第2页浏览型号SY100E212JC的Datasheet PDF文件第3页浏览型号SY100E212JC的Datasheet PDF文件第4页 
3-BIT SCANNABLE  
REGISTER  
SY10E212  
SY100E212  
DESCRIPTION  
FEATURES  
Scannable version E112 driver  
Extended 100E VEE range of –4.2V to –5.5V  
1025ps max. CLK to Output  
Dual differential outputs  
The SY10/100E212 are scannable registered ECL  
drivers typically used as fan-out memory address drivers  
for ECL cache driving. In a VLSI array-based CPU design,  
use of the E212 allows the user to conserve array output  
cell functionality and also output pins.  
Master Reset  
The input shift register is designed with control logic  
which greatly facilitates its use in boundary scan  
applications.  
Internal 75Kinput pull-down resistors  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Fully compatible with Motorola MC10E/100E212  
Available in 28-pin PLCC package  
PIN CONFIGURATION  
BLOCK DIAGRAM  
S-OUT  
25  
24 23 22 21 20 19  
Q
Q
2b  
2a  
D
D
D
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
LOAD  
CLK  
D2  
Q2b  
Q2a  
VCC  
Q1b  
Q1a  
Q1b  
Q1a  
Q
Q
Q
Q
Q
2a  
2b  
D
D
D
2
1
0
TOP VIEW  
PLCC  
VEE  
D1  
J28-1  
2
Q
Q
1b  
1a  
3
D0  
4
S-IN  
Q
Q
1a  
1b  
5
6
7
8
9
10 11  
Q
Q
0b  
0a  
Q
Q
0a  
0b  
S-IN  
LOAD  
SHIFT  
CLK  
PIN NAMES  
Pin  
D0 – D2  
S-IN  
Function  
Data Inputs  
Scan Input  
MR  
LOAD  
LOAD/HOLD Control  
Scan Control  
Clock  
SHIFT  
CLK  
MR  
Master Reset  
Scan Output  
True Outputs  
Inverting Outputs  
VCC to Output  
S-OUT  
Q[0:2]a, Q[0:2]b  
Q[0:2]a, Q[0:2]b  
VCCO  
Rev.: C  
Amendment:/1  
Issue Date: February, 1998  
1

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