SY100E175

更新时间： 2024-11-19 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		锁存器
页数	文件大小	规格书
4页	63K
描述
9-BIT LATCH WITH PARITY

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中文翻译

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数据手册

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SY100E175 数据手册

9-BIT LATCH

WITH PARITY

SY10E175

SY100E175

FEATURES

DESCRIPTION

■ 9-bit latch

The SY10/100E175 are 9-bit latches. They also feature

a tenth latched output (ODDPAR) which is formed as the

odd parity of the nine data inputs (ODDPAR is HIGH if

an odd number of the inputs are HIGH).

The E175 can also be used to generate byte parity by

using D8 as the parity-type select (L = even parity, H =

odd parity) and using ODDPAR as the byte parity output.

The LEN pin latches the data when asserted with a

logical high and makes the latch transparent when placed

at a logic low level.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Parity detection/generation

■ 800ps max. D to Output

■ Reset

■ Internal 75KΩ input pull-down resistors

■ Fully compatible with Motorola MC10E/100E175

■ Available in 28-pin PLCC package

PIN CONFIGURATION

BLOCK DIAGRAM

24 23 22 21 20 19

bits

1 – 7

TOP VIEW

PLCC

J28-1

LEN

CCO

10 11

ODDPAR

PIN NAMES

LEN

D0 – D8

LEN

Function

Data Inputs

Latch Enable

Master Reset

Data Outputs

Parity Output

VCC to Output

Q0 – Q8

ODDPAR

VCCO

Rev.: C

Amendment:/1

Issue Date: February, 1998

12 3 4

中文翻译

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