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SY100E171JCTR PDF预览

SY100E171JCTR

更新时间: 2024-11-20 20:32:23
品牌 Logo 应用领域
美国微芯 - MICROCHIP 逻辑集成电路
页数 文件大小 规格书
4页 58K
描述
Multiplexer, 100E Series, 3-Func, 4 Line Input, 1 Line Output, Complementary Output, ECL, PQCC28

SY100E171JCTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.3
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0逻辑集成电路类型:MULTIPLEXER
功能数量:3输入次数:4
输出次数:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
电源:-4.5 V最大电源电流(ICC):77 mA
Prop。Delay @ Nom-Sup:0.65 ns传播延迟(tpd):0.85 ns
认证状态:Not Qualified子类别:Multiplexer/Demultiplexers
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUADBase Number Matches:1

SY100E171JCTR 数据手册

 浏览型号SY100E171JCTR的Datasheet PDF文件第2页浏览型号SY100E171JCTR的Datasheet PDF文件第3页浏览型号SY100E171JCTR的Datasheet PDF文件第4页 
3-BIT 4:1  
SY10E171  
SY100E171  
MULTIPLEXER  
DESCRIPTION  
FEATURES  
725ps max. D to output  
The SY10/100E171 offer three 4:1 multiplexers with  
differential outputs, designed for use in new, high-  
performance ECL systems. The leading 4-bit multiplexer  
operation is organized pairwise, with each pair being a 2-  
bit multiplexer. Separate select (SEL1A, SEL1B) controls  
are provided within each pair. The SEL1A and SEL1B  
signals control the leading multiplexers, while the SEL2  
signal controls the output multiplexer. The three select  
signals can be used to determine which of the four data  
inputs will be propagated to the corresponding outputs.  
Extended 100E VEE range of –4.2V to –5.5V  
Differential outputs  
Split select architecture  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E171  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
D0x–D2x  
SEL1A, SEL1B  
SEL2  
Function  
Data Inputs  
2:1  
MUX  
SEL  
D
0a  
0b  
D
First-stage Select Inputs  
Second-stage Select Input  
True Output  
2:1  
MUX  
SEL  
Q
0
0
Q
2:1  
MUX  
SEL  
Q0–Q2  
D
0c  
Q0–Q2  
Inverted Output  
D0d  
VCCO  
VCC to Output  
2:1  
MUX  
SEL  
D
1a  
1b  
D
2:1  
MUX  
SEL  
Q
1
1
Q
2:1  
MUX  
SEL  
D
1c  
D1d  
2:1  
MUX  
SEL  
D
2a  
2b  
D
2:1  
MUX  
SEL  
Q
2
2
Q
2:1  
MUX  
SEL  
D
2c  
D2d  
SEL1A  
SEL1B  
SEL  
2
Rev.: E  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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