SY100E171

更新时间： 2024-11-19 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		转换器
页数	文件大小	规格书
4页	63K
描述
3-BIT 4:1 MULTIPLEXER

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中文翻译

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数据手册

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SY100E171 数据手册

3-BIT 4:1

MULTIPLEXER

SY10E171

SY100E171

FEATURES

DESCRIPTION

■ 725ps max. D to output

The SY10/100E171 offer three 4:1 multiplexers with

differential outputs, designed for use in new, high-

performance ECL systems. The leading 4-bit multiplexer

operation is organized pairwise, with each pair being a 2-

bit multiplexer. Separate select (SEL1A, SEL1B) controls

are provided within each pair. The SEL1A and SEL1B

signals control the leading multiplexers, while the SEL2

signal controls the output multiplexer. The three select

signals can be used to determine which of the four data

inputs will be propagated to the corresponding outputs.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Differential outputs

■ Split select architecture

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E171

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN CONFIGURATION

2:1

MUX

SEL

2:1

MUX

SEL

24 23 22 21 20 19

SEL1A

SEL1B

2:1

MUX

SEL

D0d

SEL

TOP VIEW

PLCC

2:1

MUX

SEL

J28-1

CCO

2:1

MUX

SEL

10 11

2:1

MUX

SEL

D1d

2:1

MUX

SEL

2:1

MUX

SEL

PIN NAMES

2:1

MUX

SEL

D0x–D2x

SEL1A, SEL1B

SEL2

Function

Data Inputs

D2d

First-stage Select Inputs

Second-stage Select Input

True Output

SEL1A

SEL1B

Q0–Q2

Inverted Output

SEL

VCCO

VCC to Output

Rev.: C

Amendment: /1

Issue Date: February, 1998

12 3 4

中文翻译

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