5秒后页面跳转
SY100E171JCTR PDF预览

SY100E171JCTR

更新时间: 2024-11-19 22:42:35
品牌 Logo 应用领域
麦瑞 - MICREL 转换器解复用器逻辑集成电路
页数 文件大小 规格书
4页 63K
描述
3-BIT 4:1 MULTIPLEXER

SY100E171JCTR 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.3
Is Samacsys:N系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
逻辑集成电路类型:MULTIPLEXER功能数量:3
输入次数:4输出次数:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TAPE AND REEL电源:-4.5 V
最大电源电流(ICC):77 mAProp。Delay @ Nom-Sup:0.65 ns
传播延迟(tpd):0.85 ns认证状态:Not Qualified
子类别:Multiplexer/Demultiplexers表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

SY100E171JCTR 数据手册

 浏览型号SY100E171JCTR的Datasheet PDF文件第2页浏览型号SY100E171JCTR的Datasheet PDF文件第3页浏览型号SY100E171JCTR的Datasheet PDF文件第4页 
3-BIT 4:1  
MULTIPLEXER  
SY10E171  
SY100E171  
FEATURES  
DESCRIPTION  
725ps max. D to output  
The SY10/100E171 offer three 4:1 multiplexers with  
differential outputs, designed for use in new, high-  
performance ECL systems. The leading 4-bit multiplexer  
operation is organized pairwise, with each pair being a 2-  
bit multiplexer. Separate select (SEL1A, SEL1B) controls  
are provided within each pair. The SEL1A and SEL1B  
signals control the leading multiplexers, while the SEL2  
signal controls the output multiplexer. The three select  
signals can be used to determine which of the four data  
inputs will be propagated to the corresponding outputs.  
Extended 100E VEE range of –4.2V to –5.5V  
Differential outputs  
Split select architecture  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E171  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN CONFIGURATION  
2:1  
MUX  
SEL  
D
0a  
0b  
D
2:1  
MUX  
SEL  
Q
0
0
25  
24 23 22 21 20 19  
Q
SEL1A  
SEL1B  
18  
17  
16  
15  
14  
13  
12  
26  
27  
28  
1
Q
Q
2
2
2:1  
MUX  
SEL  
D
0c  
D0d  
SEL  
2
V
CC  
TOP VIEW  
PLCC  
V
EE  
Q
Q
1
1
NC  
NC  
2
2:1  
MUX  
SEL  
D
1a  
1b  
J28-1  
3
V
CCO  
D
2:1  
MUX  
SEL  
Q
1
1
D
1c  
4
Q
0
5
6
7
8
9
10 11  
Q
2:1  
MUX  
SEL  
D
1c  
D1d  
2:1  
MUX  
SEL  
D
2a  
2b  
D
2:1  
MUX  
SEL  
Q
2
2
PIN NAMES  
Q
2:1  
MUX  
SEL  
D
2c  
Pin  
D0x–D2x  
SEL1A, SEL1B  
SEL2  
Function  
Data Inputs  
D2d  
First-stage Select Inputs  
Second-stage Select Input  
True Output  
SEL1A  
SEL1B  
Q0–Q2  
Q0–Q2  
Inverted Output  
SEL  
2
VCCO  
VCC to Output  
Rev.: C  
Amendment: /1  
Issue Date: February, 1998  
1

与SY100E171JCTR相关器件

型号 品牌 获取价格 描述 数据表
SY100E171JZ MICREL

获取价格

3-BIT 4:1 MULTIPLEXER
SY100E171JZTR MICREL

获取价格

3-BIT 4:1 MULTIPLEXER
SY100E171JZTR MICROCHIP

获取价格

Multiplexer, 100E Series, 3-Func, 4 Line Input, 1 Line Output, Complementary Output, ECL,
SY100E175 MICREL

获取价格

9-BIT LATCH WITH PARITY
SY100E175JC MICREL

获取价格

9-BIT LATCH WITH PARITY
SY100E175JCTR MICREL

获取价格

9-BIT LATCH WITH PARITY
SY100E175JCTR MICROCHIP

获取价格

D Latch, 100E Series, 1-Func, Low Level Triggered, 9-Bit, True Output, ECL, PQCC28, PLASTI
SY100E175JZ MICREL

获取价格

9-BIT LATCH WITH PARITY
SY100E175JZTR MICROCHIP

获取价格

D Latch, 100E Series, 1-Func, Low Level Triggered, 9-Bit, True Output, ECL, PQCC28, LEAD F
SY100E175JZTR MICREL

获取价格

9-BIT LATCH WITH PARITY