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ST9435GP PDF预览

ST9435GP

更新时间: 2024-11-18 17:15:43
品牌 Logo 应用领域
司坦森 - STANSON /
页数 文件大小 规格书
6页 360K
描述
TO-220

ST9435GP 数据手册

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ST9435GP  
P Channel Enhancement Mode MOSFET  
ꢀ15.0A  
DESCRIPTION  
ST9435GP is the PꢀChannel logic enhancement mode power field effect transistor  
which is produced using high cell density, DMOS trench technology.  
This high density process is especially tailored to minimize onꢀstate resistance.  
These device is particularly suited for low voltage application, notebook computer  
power management and other battery circuits where highꢀside switching.  
PIN CONFIGURATION  
FEATURE  
ꢀ30V/ꢀ10A, RDS(ON) = 50mꢁ  
@VGS = ꢀ10V  
ꢀ30V/ꢀ5A, RDS(ON) = 80mꢁ  
@VGS = ꢀ4.5V  
Super high density cell design for  
extremely low RDS(ON)  
Exceptional onꢀresistance and  
maximum DC current capability  
TOꢀ220 package design  
ABSOULTE MAXIMUM RATINGS (Ta = 25 Unless otherwise noted )  
Symb  
ol  
Parameter  
DrainꢀSource Voltage  
Typical  
Unit  
VDSS  
ꢀ30  
V
V
GateꢀSource Voltage  
VGSS  
ID  
±20  
Continuous Drain Current  
TA=25℃  
ꢀ15.0  
ꢀ8.0  
A
A
(TJ=150 )  
TA=100  
Pulsed Drain Current  
IDM  
PD  
ꢀ60  
Power Dissipation  
TA=25℃  
62.5  
W
Operation Junction Temperature  
Storgae Temperature Range  
TJ  
ꢀ55/150  
ꢀ55/150  
TSTG  
Thermal ResistanceꢀJunction to Ambient  
RθJA  
62  
/W  
STANSON TECHNOLOGY  
120 Bentley Square, Mountain View, Ca 94040 USA  
www.stansontech.com  
Copyright © 2009, Stanson Corp.  
ST9435GP 2010. V1  

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