SY100E151JZTR

更新时间： 2024-02-12 03:49:49

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	63K
描述
6-BIT D REGISTER

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数据手册

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SY100E151JZTR 数据手册

SY10E151

Micrel, Inc.

SY100E151

6-BIT D

SY10E151

SY100E151

DESCRIPTION

FEATURES

■ 1100MHz toggle frequency

■ Extended 100E VEE range of –4.2V to –5.46V

■ Differential outputs

The SY10/100E151 offer 6 edge-triggered, high-speed,

master-slave D-type flip-flops with differential outputs,

designed for use in new, high-performance ECL systems.

The two external clock signals (CLK1, CLK2) are gated

through a logical OR operation before use as clocking

control for the flip-flops. Data is clocked into the flip-flops

on the rising edge of either CLK1 or CLK2 (or both). When

both CLK1 and CLK2 are at a logic LOW, data enters the

master and is transferred to the slave when either CLK1 or

CLK2 (or both) go HIGH.

■ Asynchronous Master Reset

■ Dual clocks

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E151

■ Available in 28-pin PLCC package

The MR (Master Reset) signal operates asynchronously

to make all Q outputs go to a logic LOW.

BLOCK DIAGRAM

PIN NAMES

D0–D5

CLK1, CLK2

Function

Data Inputs

Clock Inputs

Master Reset

True Outputs

Inverting Outputs

VCC to Output

Q0–Q5

VCCO

CLK

Rev.: G

Amendment: /0

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

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