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SY100E154JC PDF预览

SY100E154JC

更新时间: 2024-01-29 06:33:48
品牌 Logo 应用领域
麦瑞 - MICREL 触发器逻辑集成电路
页数 文件大小 规格书
4页 64K
描述
5-BIT 2:1 MUX-LATCH

SY100E154JC 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.7
其他特性:FIVE 2:1 MUX FOLLOWED BY LATCH系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:D LATCH
湿度敏感等级:2位数:5
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245传播延迟(tpd):0.75 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
触发器类型:LOW LEVEL宽度:11.48 mm
Base Number Matches:1

SY100E154JC 数据手册

 浏览型号SY100E154JC的Datasheet PDF文件第2页浏览型号SY100E154JC的Datasheet PDF文件第3页浏览型号SY100E154JC的Datasheet PDF文件第4页 
5-BIT 2:1  
MUX-LATCH  
SY10E154  
SY100E154  
FEATURES  
DESCRIPTION  
750ps max. LEN to output  
Extended 100E VEE range of –4.2V to –5.5V  
700ps max. D to output  
The SY10/100E154 offer five 2:1 multiplexers followed  
by latches with differential outputs, designed for use in  
new, high-performance ECL systems. The two external  
Latch-Enable signals (LEN1, LEN2) are gated through a  
logical OR operation before use as control for the five  
latches. When both LEN1 and LEN2 are at a logic LOW, the  
latches are transparent, thus presenting the data from the  
multiplexers at the output pins. If either LEN1 or LEN2 (or  
both) are at a logic HIGH, the outputs are latched.  
ThemultiplexeroperationiscontrolledbytheSEL(Select)  
signal which selects one of the two bits of input data at each  
mux to be passed through.  
Differential outputs  
Asynchronous Master Reset  
Dual latch-enables  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E154  
Available in 28-pin PLCC package  
The MR (Master Reset) signal operates asynchronously  
to make all Q outputs go to a logic LOW.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
D
D
D
D
D
D
D
D
D
D
0a  
0b  
1a  
1b  
2a  
2b  
3a  
3b  
4a  
4b  
Q
0
0
Q
Q
D
MUX  
SEL  
E
N
25 24 23 22 21 20 19  
Q
R
R
R
R
R
SEL  
LEN  
LEN  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q3  
1
Q
3
Q
1
1
D
Q
Q
2
VCC  
PLCC  
TOP VIEW  
J28-1  
MUX  
SEL  
E
N
VEE  
Q
Q
Q
Q
2
2
1
1
Q
MR  
2
D
D
0a  
3
Q
2
2
D
Q
Q
0b  
4
MUX  
SEL  
5
6
7
8
9
10 11  
E
N
Q
Q
3
3
D
Q
Q
MUX  
SEL  
E
N
Q
PIN NAMES  
Q
4
4
D
Q
Q
MUX  
SEL  
Pin  
D0a–D4a  
D0b–D4b  
SEL  
Function  
E
N
Q
Input Data a  
Input Data b  
SEL  
Data Select Input  
Latch Enables  
Master Reset  
LEN  
1
LEN1, LEN2  
MR  
LEN  
2
MR  
Q0–Q4  
Q0–Q4  
VCCO  
True Outputs  
Inverted Outputs  
VCC to Output  
Rev.: C  
Amendment: /1  
Issue Date: February, 1998  
1

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