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SY100E150JZ-TR PDF预览

SY100E150JZ-TR

更新时间: 2024-11-23 15:53:15
品牌 Logo 应用领域
美国微芯 - MICROCHIP 输出元件逻辑集成电路触发器
页数 文件大小 规格书
4页 59K
描述
100E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28

SY100E150JZ-TR 技术参数

生命周期:Active包装说明:QCCJ,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:D LATCH
位数:6功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):0.7 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD触发器类型:LOW LEVEL
宽度:11.48 mmBase Number Matches:1

SY100E150JZ-TR 数据手册

 浏览型号SY100E150JZ-TR的Datasheet PDF文件第2页浏览型号SY100E150JZ-TR的Datasheet PDF文件第3页浏览型号SY100E150JZ-TR的Datasheet PDF文件第4页 
0  
0  
6-BIT D  
LATCH  
SY10E150  
SY100E150  
DESCRIPTION  
FEATURES  
700ps max. propagation delay  
Extended 100E VEE range of –4.2V to –5.5V  
Differential outputs  
The SY10/100E150 are 6-bit D latches with differential  
outputs designed for use in new, high- performance ECL  
systems. When both Latch Enables (LEN1, LEN2) are at a  
logic LOW, the latch is in the transparent mode and input  
data propagates through to the output. A logic HIGH on  
either LEN1 or LEN2 (or both) latches the input data. The  
Master Reset (MR) overrides all other signals to set the Q  
outputs to a logic LOW.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E150  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
D0–D5  
LEN1, LEN2  
MR  
Function  
Data Inputs  
D0  
D1  
D2  
D3  
D4  
D5  
Q
0
0
D
D
R
R
R
R
R
R
Q
Latch Enables  
Master Reset  
True Outputs  
Inverting Outputs  
VCC to Output  
Q
1
1
Q0–Q5  
Q0–Q5  
VCCO  
Q
Q
2
2
D
D
D
D
Q
Q
3
3
Q
Q
4
4
Q
Q
5
5
Q
LEN  
1
2
LEN  
MR  
Rev.: F  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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