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SY100E141JYTR PDF预览

SY100E141JYTR

更新时间: 2024-11-19 06:15:11
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器
页数 文件大小 规格书
4页 63K
描述
8-BIT SHIFT REGISTER

SY100E141JYTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.2计数方向:BIDIRECTIONAL
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT湿度敏感等级:2
位数:8功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260传播延迟(tpd):0.975 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:700 MHzBase Number Matches:1

SY100E141JYTR 数据手册

 浏览型号SY100E141JYTR的Datasheet PDF文件第2页浏览型号SY100E141JYTR的Datasheet PDF文件第3页浏览型号SY100E141JYTR的Datasheet PDF文件第4页 
8-BIT SHIFT  
REGISTER  
SY10E141  
SY100E141  
FEATURES  
DESCRIPTION  
700MHz min. shift frequency  
Extended 100E VEE range of –4.2V to –5.5V  
8 bits wide  
The SY10/100E141 are 8-bit, full-function shift registers  
designed for use in new, high-performance ECL systems.  
The E141 performs serial/parallel in and serial/parallel out,  
shifting in either direction. The eight inputs D0–D7 accept  
parallel input data, while DL/DR accept serial input data for  
left/right shifting.  
The two select pins, SEL0 and SEL1 permit four modes  
of operation: Load, Hold, Shift Left and Shift Right, as  
shown in the Truth Table. Input data is clocked into the  
register on the rising clock edge after meeting the minimum  
set-up time. A logic HIGH on the Master Reset (MR) pin  
asynchronously resets all the registers to zero.  
Bi-directional  
Four selectable modes for full functionality  
Asynchronous Master Reset  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E141  
Pin-compatible with E241  
Available in 28-pin PLCC package  
PIN NAMES  
Pin  
D0-D7  
Function  
Parallel Data Inputs  
Serial Data Inputs  
Mode Select Inputs  
Clock  
DL, DR  
SEL0, SEL1  
CLK  
Q0-Q7  
MR  
Data Outputs  
Master Reset  
VCCO  
VCC to Output  
BLOCK DIAGRAM  
DL  
BITS 1-6  
D
Q
R
Q
R
D
D
Q
R
DR  
D0  
Q7  
Q0  
Q
D
D7  
SEL1  
SEL0  
CLK  
MR  
Rev.: E  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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