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SY100E142JCTR PDF预览

SY100E142JCTR

更新时间: 2024-01-21 06:15:28
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
4页 75K
描述
9-BIT SHIFT REGISTER

SY100E142JCTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.51
Is Samacsys:N其他特性:SIPO OPERATION ALSO AVAILABLE
计数方向:RIGHT系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
湿度敏感等级:2位数:9
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260最大电源电流(ICC):165 mA
传播延迟(tpd):1 ns认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压 (Vsup):-5.5 V
最小供电电压 (Vsup):-4.2 V表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:700 MHz
Base Number Matches:1

SY100E142JCTR 数据手册

 浏览型号SY100E142JCTR的Datasheet PDF文件第2页浏览型号SY100E142JCTR的Datasheet PDF文件第3页浏览型号SY100E142JCTR的Datasheet PDF文件第4页 
9-BIT SHIFT  
REGISTER  
SY10E142  
SY100E142  
FEATURES  
DESCRIPTION  
700MHz min. shift frequency  
Extended 100E VEE range of –4.2V to –5.5V  
9 bits wide for byte-parity applications  
Asynchronous Master Reset  
Dual clocks  
The SY10/100E142 are high-speed 9-bit shift registers  
designed for use in new, high-performance ECL systems.  
The E142 can accept serial or parallel data to be shifted out  
in one direction as both serial and parallel outputs. The  
nine inputs, D0-D8, accept parallel input data, while S-IN  
accepts serial input data.  
The SEL (Select) control pin serves to determine the  
modeofoperation, eitherSHIFTorLOAD. Theshiftdirection  
is from bit 0 to bit 8. The input data has to meet the set-up  
time before being clocked into the nine input registers on  
the rising edge of CLK1 or CLK2. Shifting is also performed  
on the rising edge of either CLK1 or CLK2. The MR (Master  
Reset) control signal asynchronously resets all nine  
registers to a logic LOW when a logic HIGH is applied to  
MR.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E142  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
The E142 is designed for applications such as diagnostic  
scan registers, parallel-to-serial conversions and is also  
suitable for byte-wide parity.  
S-IN  
D0  
1
0
D Q  
D Q  
D Q  
D Q  
D Q  
D Q  
D Q  
Q0  
Q1  
PIN CONFIGURATION  
1
0
D1  
1
0
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
D2  
D3  
25 24 23 22 21 20 19  
MR  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q7  
1
0
CLK  
1
Q
6
CLK  
2
VCC  
PLCC  
TOP VIEW  
J28-1  
VEE  
Q
5
S-IN  
1
0
2
VCCO  
D
D
0
1
3
Q
Q
4
3
D4  
D5  
D6  
4
5
6
7
8
9
10 11  
1
0
1
0
PIN NAMES  
1
0
D Q  
D Q  
Pin  
D0-D8  
S-IN  
Function  
D7  
Parallel Data Inputs  
Serial Data Input  
Mode Select Input  
Clock Inputs  
1
0
SEL  
D8  
CLK1, CLK2  
MR  
SEL  
Master Reset  
CLK1  
CLK2  
Q0-Q8  
VCCO  
Data Outputs  
MR  
VCC to Output  
Rev.: C  
Amendment: /1  
Issue Date: February, 1998  
1

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