SY100E143JCTR

更新时间： 2024-01-10 17:52:57

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	75K
描述
9-BIT HOLD REGISTER

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数据手册

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SY100E143JCTR 数据手册

9-BIT HOLD

SY10E143

SY100E143

DESCRIPTION

FEATURES

The SY10/100E143 are high-speed 9-bit hold registers

designed for use in new, high-performance ECL systems.

The E143 can hold current data or load new data. The nine

inputs, D0-D8, accept parallel input data.

The SEL (Select) control pin serves to determine the

mode of operation; either HOLD or LOAD. The input data

has to meet the set-up time before being clocked into the

nine input registers on the rising edge of CLK1 or CLK2.

The MR (Master Reset) control signal asynchronously

resets all nine registers to a logic LOW when a logic HIGH

is applied to MR.

■ 700MHz min. operating frequency

■ Extended 100E VEE range of –4.2V to –5.5V

■ 9 bits wide for byte-parity applications

■ Asynchronous Master Reset

■ Dual clocks

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75kΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E143

■ Available in 28-pin PLCC package

The E143 is designed for applications requiring high-

speed registers, pipeline registers, synchronous operation,

and is also suitable for byte-wide parity.

BLOCK DIAGRAM

PIN CONFIGURATION

MUX

25 24 23 22 21 20 19

CLK

VCC

PLCC

TOP VIEW

J28-1

VEE

MUX

VCCO

10 11

MUX

PIN NAMES

MUX

D0-D8

SEL

Function

Parallel Data Inputs

Mode Select Input

Clock Inputs

CLK1, CLK2

Master Reset

Q0-Q8

Data Outputs

SEL

CLK1

CLK2

No Connection

VCC to Output

VCCO

Rev.: D

Amendment: /0

Issue Date: August, 1998

12 3 4

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