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SY100E143JC PDF预览

SY100E143JC

更新时间: 2024-11-22 22:15:15
品牌 Logo 应用领域
麦瑞 - MICREL 触发器锁存器逻辑集成电路
页数 文件大小 规格书
4页 75K
描述
9-BIT HOLD REGISTER

SY100E143JC 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ,Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.27
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.48 mm
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:1
位数:9功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):240
传播延迟(tpd):1 ns认证状态:Not Qualified
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:700 MHz
Base Number Matches:1

SY100E143JC 数据手册

 浏览型号SY100E143JC的Datasheet PDF文件第2页浏览型号SY100E143JC的Datasheet PDF文件第3页浏览型号SY100E143JC的Datasheet PDF文件第4页 
9-BIT HOLD  
REGISTER  
SY10E143  
SY100E143  
DESCRIPTION  
FEATURES  
The SY10/100E143 are high-speed 9-bit hold registers  
designed for use in new, high-performance ECL systems.  
The E143 can hold current data or load new data. The nine  
inputs, D0-D8, accept parallel input data.  
The SEL (Select) control pin serves to determine the  
mode of operation; either HOLD or LOAD. The input data  
has to meet the set-up time before being clocked into the  
nine input registers on the rising edge of CLK1 or CLK2.  
The MR (Master Reset) control signal asynchronously  
resets all nine registers to a logic LOW when a logic HIGH  
is applied to MR.  
700MHz min. operating frequency  
Extended 100E VEE range of –4.2V to –5.5V  
9 bits wide for byte-parity applications  
Asynchronous Master Reset  
Dual clocks  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E143  
Available in 28-pin PLCC package  
The E143 is designed for applications requiring high-  
speed registers, pipeline registers, synchronous operation,  
and is also suitable for byte-wide parity.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
D
D
Q0  
MUX  
D0  
D1  
D2  
R
R
Q1  
Q2  
MUX  
MUX  
25 24 23 22 21 20 19  
MR  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q7  
D
D
CLK  
1
Q
6
R
R
CLK  
2
VCC  
PLCC  
TOP VIEW  
J28-1  
VEE  
Q
5
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
NC  
MUX  
2
VCCO  
D3  
D4  
D5  
D6  
D7  
D8  
D
D
0
1
3
Q
Q
4
3
4
D
D
5
6
7
8
9
10 11  
MUX  
MUX  
R
R
D
D
PIN NAMES  
MUX  
MUX  
MUX  
R
R
Pin  
D0-D8  
SEL  
Function  
Parallel Data Inputs  
Mode Select Input  
Clock Inputs  
CLK1, CLK2  
MR  
D
Master Reset  
R
Q0-Q8  
NC  
Data Outputs  
SEL  
CLK1  
CLK2  
No Connection  
VCC to Output  
VCCO  
MR  
Rev.: D  
Amendment: /0  
Issue Date: August, 1998  
1

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