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SY100E142JC PDF预览

SY100E142JC

更新时间: 2024-01-19 16:04:49
品牌 Logo 应用领域
美国微芯 - MICROCHIP 逻辑集成电路触发器
页数 文件大小 规格书
4页 97K
描述
Parallel In Parallel Out, 100E Series, 9-Bit, Right Direction, True Output, ECL, PQCC28, PLASTIC, LCC-28

SY100E142JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.51
其他特性:SIPO OPERATION ALSO AVAILABLE计数方向:RIGHT
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.48 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:700000000 Hz
湿度敏感等级:1位数:9
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):240
电源:-4.5 V传播延迟(tpd):1 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Shift Registers表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:700 MHz
Base Number Matches:1

SY100E142JC 数据手册

 浏览型号SY100E142JC的Datasheet PDF文件第2页浏览型号SY100E142JC的Datasheet PDF文件第3页浏览型号SY100E142JC的Datasheet PDF文件第4页 
NOT RECOMMENDED FOR NEW DESIGNS  
SY10E142  
9-BIT SHIFT  
REGISTER  
SY100E142  
FEATURES  
DESCRIPTION  
700MHz min. shift frequency  
Extended 100E VEE range of –4.2V to –5.5V  
9 bits wide for byte-parity applications  
Asynchronous Master Reset  
Dual clocks  
The SY10/100E142 are high-speed 9-bit shift registers  
designed for use in new, high-performance ECL systems.  
The E142 can accept serial or parallel data to be shifted out  
in one direction as both serial and parallel outputs. The  
nine inputs, D0-D8, accept parallel input data, while S-IN  
accepts serial input data.  
The SEL (Select) control pin serves to determine the  
modeofoperation, eitherSHIFTorLOAD. Theshiftdirection  
is from bit 0 to bit 8. The input data has to meet the set-up  
time before being clocked into the nine input registers on  
the rising edge of CLK1 or CLK2. Shifting is also performed  
on the rising edge of either CLK1 or CLK2. The MR (Master  
Reset) control signal asynchronously resets all nine  
registers to a logic LOW when a logic HIGH is applied to  
MR.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E142  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
The E142 is designed for applications such as diagnostic  
scan registers, parallel-to-serial conversions and is also  
suitable for byte-wide parity.  
S-IN  
D0  
1
0
D Q  
D Q  
D Q  
D Q  
D Q  
D Q  
D Q  
Q0  
Q1  
1
0
PIN NAMES  
D1  
Pin  
D0-D8  
S-IN  
Function  
1
0
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Parallel Data Inputs  
Serial Data Input  
Mode Select Input  
Clock Inputs  
D2  
D3  
SEL  
1
0
CLK1, CLK2  
MR  
Master Reset  
1
0
Q0-Q8  
VCCO  
Data Outputs  
D4  
D5  
D6  
VCC to Output  
1
0
1
0
1
0
D Q  
D Q  
D7  
1
0
D8  
SEL  
CLK1  
CLK2  
MR  
Rev.: E  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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