SY100E137

更新时间： 2024-11-18 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		计数器
页数	文件大小	规格书
4页	79K
描述
8-BIT RIPPLE COUNTER

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中文翻译

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数据手册

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SY100E137 数据手册

8-BIT RIPPLE

COUNTER

SY10E137

SY100E137

FEATURES

DESCRIPTION

■ 1.8GHz min. count frequency

The SY10/100E137 are very high speed binary ripple

counters. The two least significant bits were designed

with very fast edge rates, while the more significant bits

maintain standard ECLinPS output edge rates. This allows

the counters to operate at very high frequencies, while

maintaining a moderate power dissipation level.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Synchronous and asynchronous enable pins

■ Differential clock input and data output pins

■ VBB output for single-ended use

The devices are ideally suited for multiple frequency

clock generation, as well as for counters in high-

performance ATE time measurement boards.

■ Asynchronous Master Reset

■ Internal 75KΩ input pull-down resistors

■ Available in 28-pin PLCC packge

Both asynchronous and synchronous enables are

available to maximize the device's flexibility for various

applications. The asynchronous enable input, A_Start,

when asserted, enables the counter while overriding any

synchronous enable signals. The E137 features XOR'ed

enable inputs, EN1 and EN2, which are synchronous to

the CLK input. When only one synchronous enable is

asserted, the counter becomes disabled on the next CLK

transition. All outputs remain in the previous state poised

for the other synchronous enable or A_Start to be

asserted in order to re-enable the counter. Asserting

both synchronous enables causes the counter to become

enabled on the next transition of the CLK. EN1 (or EN2)

and CLK edges are coincident. Sufficient delay has been

inserted in the CLK path (to compensate for the XOR

gate delay and the internal D-flip-flop set-up time) to

ensure that the synchronous enable signal is clocked

correctly; hence, the counter is disabled.

PIN CONFIGURATION

25 24 23 22 21 20 19

A_Start

VCC

PLCC

TOP VIEW

J28-1

VEE

CLK

VBB

10 11

The E137 can also be driven single-endedly utilizing

the VBB output supply as the voltage reference for the

CLK input signal. If a single-ended signal is to be used,

the VBB pin should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. VBB can

only source/sink 0.5mA; therefore, it should be used as

a switching reference for the E137 only.

All input pins left open will be pulled LOW via an input

pull-down resistor. Therefore, do not leave the differential

CLK inputs open. Doing so causes the current source

transistor of the input clock gate to become saturated,

thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

PIN NAMES

CLK, CLK

Q0–Q7, Q0–Q7

A_Start

EN1, EN2

Function

The asynchronous Master Reset resets the counter to

an all zero state upon assertion.

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Reference Output

VCC to Output

VBB

VCCO

Rev.: C

Amendment:/1

Issue Date: February, 1998

12 3 4

中文翻译

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与SY100E137相关器件

型号	品牌	获取价格	描述	数据表
SY100E137JC	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E137JCTR	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E137JZ	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E137JZTR	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E141	MICREL	获取价格	8-BIT SHIFT REGISTER
SY100E141JC	MICREL	获取价格	8-BIT SHIFT REGISTER
SY100E141JC	MICROCHIP	获取价格	Parallel In Parallel Out, 100E Series, 8-Bit, Bidirectional, True Output, ECL, PQCC28
SY100E141JCTR	MICREL	获取价格	8-BIT SHIFT REGISTER
SY100E141JY	MICROCHIP	获取价格	100E SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQC
SY100E141JY	MICREL	获取价格	8-BIT SHIFT REGISTER

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