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SY100E141 PDF预览

SY100E141

更新时间: 2024-11-18 22:42:35
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器
页数 文件大小 规格书
4页 77K
描述
8-BIT SHIFT REGISTER

SY100E141 数据手册

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8-BIT SHIFT  
REGISTER  
SY10E141  
SY100E141  
DESCRIPTION  
FEATURES  
700MHz min. shift frequency  
Extended 100E VEE range of –4.2V to –5.5V  
8 bits wide  
The SY10/100E141 are 8-bit, full-function shift registers  
designed for use in new, high-performance ECL systems.  
The E141 performs serial/parallel in and serial/parallel out,  
shifting in either direction. The eight inputs D0–D7 accept  
parallel input data, while DL/DR accept serial input data for  
left/right shifting.  
The two select pins, SEL0 and SEL1 permit four modes  
of operation: Load, Hold, Shift Left and Shift Right, as  
shown in the Truth Table. Input data is clocked into the  
register on the rising clock edge after meeting the minimum  
set-up time. A logic HIGH on the Master Reset (MR) pin  
asynchronously resets all the registers to zero.  
Bi-directional  
Four selectable modes for full functionality  
Asynchronous Master Reset  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E141  
Pin-compatible with E241  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
DL  
BITS 1-6  
D
Q
R
Q
R
D
D
Q
R
DR  
D0  
Q7  
Q0  
Q
D
D7  
SEL1  
SEL0  
CLK  
MR  
Rev.: C  
Amendment: /1  
Issue Date: February, 1998  
1

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