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SY100E137JCTR PDF预览

SY100E137JCTR

更新时间： 2024-11-18 22:13:39
品牌 Logo 应用领域
麦瑞 - MICREL 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
4页 79K
描述
8-BIT RIPPLE COUNTER

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中文翻译

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SY100E137JCTR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.47
其他特性：COMPLEMENTARY OUTPUTS计数方向：UP
系列：100EJESD-30 代码：S-PQCC-J28
JESD-609代码：e0负载/预设输入：NO
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：1800000000 Hz
工作模式：ASYNCHRONOUS位数：8
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：OPEN-EMITTER封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
包装方法：TAPE AND REEL电源：-4.5 V
最大电源电流（ICC）：167 mA传播延迟（tpd）：4.95 ns
认证状态：Not Qualified子类别：Counters
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD触发器类型：POSITIVE EDGE
最小 fmax：2200 MHz

SY100E137JCTR 数据手册

 浏览型号SY100E137JCTR的Datasheet PDF文件第2页浏览型号SY100E137JCTR的Datasheet PDF文件第3页浏览型号SY100E137JCTR的Datasheet PDF文件第4页 
8-BIT RIPPLE  
COUNTER  
SY10E137  
SY100E137  
FEATURES  
DESCRIPTION  
■ 1.8GHz min. count frequency  
The SY10/100E137 are very high speed binary ripple  
counters. The two least significant bits were designed  
with very fast edge rates, while the more significant bits  
maintain standard ECLinPS output edge rates. This allows  
the counters to operate at very high frequencies, while  
maintaining a moderate power dissipation level.  
■ Extended 100E VEE range of –4.2V to –5.5V  
■ Synchronous and asynchronous enable pins  
■ Differential clock input and data output pins  
■ VBB output for single-ended use  
The devices are ideally suited for multiple frequency  
clock generation, as well as for counters in high-  
performance ATE time measurement boards.  
■ Asynchronous Master Reset  
■ Internal 75KΩ input pull-down resistors  
■ Available in 28-pin PLCC packge  
Both asynchronous and synchronous enables are  
available to maximize the device's flexibility for various  
applications. The asynchronous enable input, A_Start,  
when asserted, enables the counter while overriding any  
synchronous enable signals. The E137 features XOR'ed  
enable inputs, EN1 and EN2, which are synchronous to  
the CLK input. When only one synchronous enable is  
asserted, the counter becomes disabled on the next CLK  
transition. All outputs remain in the previous state poised  
for the other synchronous enable or A_Start to be  
asserted in order to re-enable the counter. Asserting  
both synchronous enables causes the counter to become  
enabled on the next transition of the CLK. EN1 (or EN2)  
and CLK edges are coincident. Sufficient delay has been  
inserted in the CLK path (to compensate for the XOR  
gate delay and the internal D-flip-flop set-up time) to  
ensure that the synchronous enable signal is clocked  
correctly; hence, the counter is disabled.  
PIN CONFIGURATION  
25 24 23 22 21 20 19  
A_Start  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q4  
EN  
1
2
Q
4
EN  
VCC  
PLCC  
TOP VIEW  
J28-1  
VEE  
Q
3
CLK  
CLK  
Q
3
2
Q
Q
2
2
3
VBB  
4
5
6
7
8
9
10 11  
The E137 can also be driven single-endedly utilizing  
the VBB output supply as the voltage reference for the  
CLK input signal. If a single-ended signal is to be used,  
the VBB pin should be connected to the CLK input and  
bypassed to ground via a 0.01µF capacitor. VBB can  
only source/sink 0.5mA; therefore, it should be used as  
a switching reference for the E137 only.  
All input pins left open will be pulled LOW via an input  
pull-down resistor. Therefore, do not leave the differential  
CLK inputs open. Doing so causes the current source  
transistor of the input clock gate to become saturated,  
thus upsetting the internal bias regulators and  
jeopardizing the stability of the device.  
PIN NAMES  
Pin  
CLK, CLK  
Q0–Q7, Q0–Q7  
A_Start  
EN1, EN2  
MR  
Function  
The asynchronous Master Reset resets the counter to  
an all zero state upon assertion.  
Differential Clock Inputs  
Differential Q Outputs  
Asynchronous Enable Input  
Synchronous Enable Inputs  
Asynchronous Master Reset  
Switching Reference Output  
VCC to Output  
VBB  
VCCO  
Rev.: C  
Amendment:/1  
Issue Date: February, 1998  
1
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中文翻译

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型号 品牌 替代类型 描述 数据表
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