SY100E131JCTR

更新时间： 2024-11-22 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		触发器
页数	文件大小	规格书
4页	77K
描述
4-BIT D FLIP-FLOP

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数据手册

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SY100E131JCTR 数据手册

4-BIT D

FLIP-FLOP

SY10E131

SY100E131

DESCRIPTION

FEATURES

■ 1100MHz min. toggle frequency

■ Extended 100E VEE range of –4.2V to –5.5V

■ Differential output

The SY10/100E131 are high-speed quad master slave

D-type flip-flops with differential outputs designed for use

in new, high-performance ECL systems. The flip-flops may

be individually clocked by holding CC (Common Clock) at

a logic LOW and then using the four individual CE (Clock

Enable CE0–CE3) inputs to accomplish such clocking.

Alternatively, all four flip-flops can be clocked in common

by holding the CE inputs LOW and then using CC to clock

the data. In the common clock mode, the CE input acts as

a control that passes the CC signal to the flip-flop. Data is

clocked into the flip-flop on the rising edge of the output of

the logical OR operation between CE and CC (data enters

the master when both CC and CE are LOW and data

transfers to the slave when either CE or CC, or both, go

HIGH).

■ Individual and common clocks

■ Indivldual asynchronous reset

■ Paired asynchronous sets

■ Fully compatible with Industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E131

■ Available in 28-pin PLCC package

Asynchronous set and reset controls are provided. The

reset controls are individual and the set controls are

pairwise.

PIN NAMES

PIN CONFIGURATION

Function

Data Inputs

D0-D3

CE0-CE3

R0-R3

Clock Enables (Individual)

Resets

25 24 23 22 21 20 19

Common Clock

Sets (paired)

S03, S12

Q0-Q3

VCCO

PLCC

TOP VIEW

J28-1

True Outputs

Inverting Outputs

VCC to Output

10 11

Rev.: E

Amendment: /0

Issue Date: November, 1998

12 3 4

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