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SST12LP08 PDF预览

SST12LP08

更新时间: 2024-09-20 12:31:27
品牌 Logo 应用领域
SST 放大器功率放大器
页数 文件大小 规格书
98页 1108K
描述
2.4 GHz High-Power, High-Gain Power Amplifier

SST12LP08 数据手册

 浏览型号SST12LP08的Datasheet PDF文件第2页浏览型号SST12LP08的Datasheet PDF文件第3页浏览型号SST12LP08的Datasheet PDF文件第4页浏览型号SST12LP08的Datasheet PDF文件第5页浏览型号SST12LP08的Datasheet PDF文件第6页浏览型号SST12LP08的Datasheet PDF文件第7页 
256Mb and 512Mb (256Mb/256Mb), P30-65nm  
Features  
Micron Parallel NOR Flash Embedded  
Memory (P30-65nm)  
JS28F256P30B/TFx, RC28F256P30B/TFx, PC28F256P30B/TFx,  
RD48F4400P0VBQEx, RC48F4400P0VB0Ex,  
PC48F4400P0VB0Ex, PF48F4000P0ZB/TQEx  
• Security  
Features  
• High performance  
– One-time programmable register: 64 OTP bits,  
programmed with unique information from Mi-  
cron; 2112 OTP bits available for customer pro-  
gramming  
– 100ns initial access for Easy BGA  
– 110ns initial access for TSOP  
– 25ns 16-word asychronous page read mode  
– 52 MHz (Easy BGA) with zero WAIT states and  
17ns clock-to-data output synchronous burst  
read mode  
– Absolute write protection: VPP = VSS  
– Power-transition erase/program lockout  
– Individual zero-latency block locking  
– Individual block lock-down  
– Password access  
• Software  
– 4-, 8-, 16-, and continuous word options for burst  
mode  
– Buffered enhanced factory programming (BEFP)  
at 2 MB/s (TYP) using a 512-word buffer  
– 1.8V buffered programming at 1.14 MB/s (TYP)  
using a 512-word buffer  
25μs (TYP) program suspend  
30μs (TYP) erase suspend  
– Flash Data Integrator optimized  
– Basic command set and extended function Inter-  
face (EFI) command set compatible  
– Common flash interface  
• Architecture  
– MLC: highest density at lowest cost  
– Asymmetrically blocked architecture  
– Four 32KB parameter blocks: top or bottom con-  
figuration  
– 128KB main blocks  
– Blank check to verify an erased block  
• Voltage and power  
• Density and Packaging  
– 56-lead TSOP package (256Mb only)  
– 64-ball Easy BGA package (256Mb, 512Mb)  
– QUAD+ and SCSP packages (256Mb, 512Mb)  
– 16-bit wide data bus  
• Quality and reliabilty  
– VCC (core) voltage: 1.7V to 2.0V  
– VCCQ (I/O) voltage: 1.7V to 3.6V  
– Standy current: 65µA (TYP) for 256Mb  
– 52 MHz continuous synchronous read current:  
21mA (TYP), 24mA (MAX)  
– JESD47 compliant  
– Operating temperature: –40°C to +85°C  
– Minimum 100,000 ERASE cycles per block  
– 65nm process technology  
PDF: 09005aef84566799  
p30_65nm_MLC_256Mb-512mb.pdf - Rev. B 8/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
© 2013 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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