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SST12LF01-QDF PDF预览

SST12LF01-QDF

更新时间： 2024-11-08 21:12:51
品牌 Logo 应用领域
芯科 - SILICON 电信电信集成电路
页数 文件大小 规格书
20页 679K
描述
Telecom Circuit, 1-Func, 4 X 4 MM, ROHS COMPLIANT, MO-220J-WGGD-4, WQFN-24

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SST12LF01-QDF 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：QFN包装说明：HVQCCN,
针数：24Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.17
JESD-30 代码：S-XQCC-N24长度：4 mm
功能数量：1端子数量：24
最高工作温度：85 °C最低工作温度：
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：0.8 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：TELECOM CIRCUIT
温度等级：OTHER端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：4 mm
Base Number Matches：1

SST12LF01-QDF 数据手册

 浏览型号SST12LF01-QDF的Datasheet PDF文件第2页浏览型号SST12LF01-QDF的Datasheet PDF文件第3页浏览型号SST12LF01-QDF的Datasheet PDF文件第4页浏览型号SST12LF01-QDF的Datasheet PDF文件第5页浏览型号SST12LF01-QDF的Datasheet PDF文件第6页浏览型号SST12LF01-QDF的Datasheet PDF文件第7页 
2.4 GHz Front-End Module  
SST12LF01  
SST12LF012.4 GHz Front-End Module  
Preliminary Specifications  
FEATURES:  
•
Gain:  
•
•
Low shut-down current (Typical 2.5 µA)  
Built-in, Ultra-low IREF power-up/down control  
– IREF <4 mA  
– Typically 12 dB gain across 2.4–2.5 GHz for  
Receiver (RX) chain.  
– Typically 29 dB gain across 2.4–2.5 GHz over tem-  
perature 0°C to +80°C for Transmitter (TX) chain.  
•
High-speed power-up/down  
– Turn on/off time (10%- 90%) <100 ns  
– Typical power-up/down delay with driver delay  
included <200 ns  
High temperature stability  
– ~1 dB gain/power variation between 0°C to +85°C  
Simple input/output matching  
Single positive power supply  
Packages available  
– 24-contact WQFN – 4mm x 4mm  
All non-Pb (lead-free) devices are RoHS compliant  
•
Low-Noise Figure  
– Typical 1.45 dB across 2.4–2.55 GHz  
50 Ω Input/Output matched along RX chain.  
IIP3  
– 3 dbm 2.4–2.55 GHz  
High linear output power:  
– >26.5 dBm P1dB  
– Meets 802.11g OFDM ACPR requirement up to  
23 dBm  
– ~3% added EVM up to 19 dBm for  
54 Mbps 802.11g signal  
•
•
•
•
•
•
•
•
– Meets 802.11b ACPR requirement up to 24 dBm  
•
•
High power-added efficiency/Low operating  
current for both 802.11g/b applications  
– ~22%/210 mA @ POUT = 22 dBm for 802.11g  
– ~26%/240 mA @ POUT = 23.5 dBm for 802.11b  
APPLICATIONS:  
•
•
•
WLAN  
Bluetooth  
Wireless Network  
Low idle current  
– ~70 mA ICQ  
PRODUCT DESCRIPTION  
The SST12LF01 is a 2.4 GHz Front-End Module (FEM)  
that combines a high-performance Low-Noise Amplifier  
(LNA) and a Power Amplifier (PA).  
achieved with only a single power supply and no external  
bias resistors or networks are required. The input and out-  
put ports are singled-ended 50 Ohm matched. RF ports  
are also DC isolated requiring no dc blocking capacitors or  
matching components to reduce system board Bill of Mate-  
rials (BOM) cost.  
Designed in compliance with IEEE 802.11 b/g applications  
and based on GaAs PHEMT/HBT technology, the  
SST12LF01 operates within the frequency range of 2.4–  
2.55 GHz at a very low DC-current consumption. There are  
two components to the FEM: the Receiver (RX) chain and  
the Transmitter (TX) chain.  
The TX chain includes a high-efficiency PA based on  
InGaP/GaAs HBT technology. The PA typically provides 30  
dB gain with 22% power-added efficiency at POUT = 22  
dBm for 802.11g and 27% power-added efficiency at POUT  
= 24 dBm for 802.11b.  
The RX chain consist of a cost effective Low-Noise Ampli-  
fier (LNA) cell which requires no external RF-matching  
components. This device is based on the 0.5m GaAs  
PHEMT technology, and complies with 802.11 b/g applica-  
tions.  
The Transmitter chain has excellent linearity, typically <4%  
added EVM up to 20 dBm output power, which is essential  
for 54 Mbps 802.11g operation while meeting 802.11g  
spectrum mask at 23 dBm.  
The LNA provides high-performance, low-noise, and mod-  
erate gain operation within the 2.4–2.55 GHz frequency  
band. Across this frequency band, the LNA typically pro-  
vides 12 dB gain and 1.45 dB noise figure.  
The SST12LF01 is offered in 24-contact WQFN package.  
See Figure 2 for pin assignments and Table 1 for pin  
descriptions.  
This LNA cell is designed with a self DC-biasing scheme,  
which maintains low DC current consumption, nominally at  
11 mA, during operation. Optimum performance is  
©2008 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71330-04-000  
1
11/08  
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