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SN74AUC2G240DCURE4 PDF预览

SN74AUC2G240DCURE4

更新时间： 2024-09-28 20:48:43
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 292K
描述
IC,BUFFER/DRIVER,SINGLE,2-BIT,AUC-CMOS,TSSOP,8PIN,PLASTIC

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SN74AUC2G240DCURE4 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSSOP, TSSOP8,.12,20Reach Compliance Code：not_compliant
风险等级：5.92控制类型：ENABLE LOW
JESD-30 代码：R-PDSO-G8负载电容（CL）：15 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.005 A
位数：2功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP8,.12,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL电源：1.2/2.5 V
Prop。Delay @ Nom-Sup：3.3 ns认证状态：Not Qualified
子类别：Bus Driver/Transceivers表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUALBase Number Matches：1

SN74AUC2G240DCURE4 数据手册

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SN74AUC2G240  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES534B–DECEMBER 2003–REVISED SEPTEMBER 2006  
FEATURES  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
±8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
– 1000-V Charged-Device Model (C101)  
•
•
•
Sub-1-V Operable  
Max tpd of 1.8 ns at 1.8 V  
Low Power Consumption, 10 µA at 1.8 V  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2Y  
2A  
VCC  
1
2
3
4
8
7
6
5
1OE  
VCC  
2OE  
1Y  
1
2
3
4
8
7
6
5
1OE  
1A  
3 6  
2 7  
1 8  
1Y  
1A  
2Y  
2OE  
1Y  
1A  
2OE  
VCC  
1OE  
2A  
GND  
2Y  
GND  
2A  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC  
operation.  
The SN74AUC2G240 is designed specifically to improve the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented receivers and transmitters.  
This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,  
the device passes data from the A input to the Y output. When OE is high, the outputs are in the  
high-impedance state.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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