SN74AUC2G34
DUAL BUFFER GATE
www.ti.com
SCES514A–NOVEMBER 2003–REVISED MARCH 2006
FEATURES
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
•
•
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
Ioff Supports Partial-Power-Down Mode
Operation
– 1000-V Charged-Device Model (C101)
•
•
•
Sub-1-V Operable
Max tpd of 1.6 ns at 1.8 V
Low Power Consumption, 10 µA at 1.8 V
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YEP PACKAGE
(BOTTOM VIEW)
1Y
VCC
2Y
1
2
3
6
5
4
1A
GND
2A
1
2
3
6
5
4
1A
GND
2A
1Y
VCC
2Y
1
2
3
6
5
4
1A
GND
2A
1Y
VCC
2Y
3
2
1
4
5
6
2Y
VCC
1Y
2A
GND
1A
DESCRIPTION/ORDERING INFORMATION
This dual buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC2G34 performs the Boolean function Y = A in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
SN74AUC2G34YEPR
_ _ _U9_
Tape and reel
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SN74AUC2G34YZPR
–40°C to 85°C
SOT-563 – DRL
SOT-23 – DBV
SC-70 – DCK
Tape and reel
Tape and reel
Tape and reel
SN74AUC2G34DRLR
SN74AUC2G34DBVR
SN74AUC2G34DCKR
U9_
U34_
U9_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.