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SN74AUC2G32DCUR PDF预览

SN74AUC2G32DCUR

更新时间: 2024-11-15 22:11:47
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
10页 232K
描述
DUAL 2 INPUT POSITIVE OR GATE

SN74AUC2G32DCUR 数据手册

 浏览型号SN74AUC2G32DCUR的Datasheet PDF文件第2页浏览型号SN74AUC2G32DCUR的Datasheet PDF文件第3页浏览型号SN74AUC2G32DCUR的Datasheet PDF文件第4页浏览型号SN74AUC2G32DCUR的Datasheet PDF文件第5页浏览型号SN74AUC2G32DCUR的Datasheet PDF文件第6页浏览型号SN74AUC2G32DCUR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢇ  
ꢊꢅꢄ ꢋ ꢇ ꢌꢍꢁ ꢎꢅꢏ ꢎꢐ ꢀꢍ ꢏ ꢍꢑꢒꢌ ꢐ ꢓ ꢈ ꢄꢏꢒ  
SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1A  
1B  
V
CC  
1
2
3
4
8
7
6
5
1Y  
2B  
2A  
2Y  
D
I
Supports Partial-Power-Down Mode  
off  
GND  
Operation  
D
D
D
D
D
Sub 1-V Operable  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Max t of 1.5 ns at 1.8 V  
pd  
Low Power Consumption, 10 µA at 1.8 V  
4 5  
3 6  
2 7  
1 8  
GND  
2Y  
1B  
2A  
2B  
1Y  
8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1A  
V
CC  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This dual 2-input positive-OR gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V  
CC  
to 1.95-V V  
operation.  
CC  
The SN74AUC2G32 performs the Boolean function Y + A ) B or Y + A B in positive logic.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of  
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74AUC2G32YEPR  
SN74AUC2G32YZPR  
Tape and reel  
_ _ _UG_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
SSOP − DCT  
Tape and reel  
Tape and reel  
SN74AUC2G32DCTR  
SN74AUC2G32DCUR  
U32_ _ _  
U32_  
VSSOP − DCU  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available  
at www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and  
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢏꢟ  
Copyright 2003, Texas Instruments Incorporated  
ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AUC2G32DCUR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC2G32DCURG4 TI

完全替代

DUAL 2-INPUT POSITIVE-OR GATE
SN74AUC2G32DCURE4 TI

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DUAL 2-INPUT POSITIVE-OR GATE

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