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SN74AUC2G32YZPR PDF预览

SN74AUC2G32YZPR

更新时间： 2024-11-15 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
10页 232K
描述
DUAL 2 INPUT POSITIVE OR GATE

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中文翻译

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SN74AUC2G32YZPR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA8,2X4,20针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.56系列：AUC
JESD-30 代码：R-PBGA-B8JESD-609代码：e1
长度：1.4 mm负载电容（CL）：15 pF
逻辑集成电路类型：OR GATE最大I（ol）：0.009 A
湿度敏感等级：1功能数量：2
输入次数：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA8,2X4,20
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/2.5 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：3.3 ns传播延迟（tpd）：3.3 ns
认证状态：Not Qualified施密特触发器：NO
座面最大高度：0.5 mm子类别：Gates
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.9 mm
Base Number Matches：1

SN74AUC2G32YZPR 数据手册

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SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1A  
1B  
V
CC  
1
2
3
4
8
7
6
5
1Y  
2B  
2A  
2Y  
D
I
Supports Partial-Power-Down Mode  
off  
GND  
Operation  
D
D
D
D
D
Sub 1-V Operable  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Max t of 1.5 ns at 1.8 V  
pd  
Low Power Consumption, 10 µA at 1.8 V  
4 5  
3 6  
2 7  
1 8  
GND  
2Y  
1B  
2A  
2B  
1Y  
8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1A  
V
CC  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This dual 2-input positive-OR gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V  
CC  
to 1.95-V V  
operation.  
CC  
The SN74AUC2G32 performs the Boolean function Y + A ) B or Y + A • B in positive logic.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of  
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74AUC2G32YEPR  
SN74AUC2G32YZPR  
Tape and reel  
_ _ _UG_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
SSOP − DCT  
Tape and reel  
Tape and reel  
SN74AUC2G32DCTR  
SN74AUC2G32DCUR  
U32_ _ _  
U32_  
VSSOP − DCU  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available  
at www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and  
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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SN74AUC2G32YZPR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC2G32YZTR TI

类似代替

 AUC SERIES, DUAL 2-INPUT OR GATE, PBGA8, ROHS COMPLIANT, DSBGA-8
SN74AUC2G32YEPR TI

功能相似

 DUAL 2 INPUT POSITIVE OR GATE

与SN74AUC2G32YZPR相关器件

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SN74AUC2G32YZTR TI

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 		AUC SERIES, DUAL 2-INPUT OR GATE, PBGA8, ROHS COMPLIANT, DSBGA-8
SN74AUC2G34 TI

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 		Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34_09 TI

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 		DUAL BUFFER GATE
SN74AUC2G34DBVR TI

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 		Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DBVRE4 TI

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 		Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DBVRG4 TI

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 		DUAL BUFFER GATE
SN74AUC2G34DCKR TI

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 		Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DCKRE4 TI

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 		Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DCKRG4 TI

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 		DUAL BUFFER GATE
SN74AUC2G34DRLR TI

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 		Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera

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