Datasheet > SN74AUC2G34DBVRG4

SN74AUC2G34DBVRG4

更新时间： 2024-09-28 06:12:55

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德州仪器 - TI		/
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DUAL BUFFER GATE

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SN74AUC2G34DBVRG4 数据手册

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SN74AUC2G34

DUAL BUFFER GATE

www.ti.com

SCES514B–NOVEMBER 2003–REVISED JANUARY 2007

FEATURES

•

Available in the Texas Instruments

NanoFree™ Package

•

Low Power Consumption, 10 µA at 1.8 V

±8-mA Output Drive at 1.8 V

•

Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

•

I_offSupports Partial-Power-Down Mode

Operation

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

•

Sub-1-V Operable

1000-V Charged-Device Model (C101)

Max t_pdof 1.6 ns at 1.8 V

DBV PACKAGE

(TOP VIEW)

DCK PACKAGE

(TOP VIEW)

DRL PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

V_CC

GND

V_CC

GND

V_CC

GND

DESCRIPTION/ORDERING INFORMATION

This dual buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC

operation.

The SN74AUC2G34 performs the Boolean function Y = A in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free)

SOT-563 – DRL

Reel of 3000

SN74AUC2G34YZPR

_ _ _U9_

Reel of 4000

Reel of 3000

SN74AUC2G34DRLR

SN74AUC2G34DBVR

SN74AUC2G34DCKR

U9_

–40°C to 85°C

SOT-23 – DBV

U34_

U9_

SC-70 – DCK

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...15

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SN74AUC2G34DBVRG4 替代型号

型号	品牌	替代类型	描述	数据表
SN74AUC2G34DBVR	TI	完全替代	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DBVRE4	TI	类似代替	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera

与SN74AUC2G34DBVRG4相关器件

型号	品牌	获取价格	描述	数据表
SN74AUC2G34DCKR	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DCKRE4	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DCKRG4	TI	获取价格	DUAL BUFFER GATE
SN74AUC2G34DRLR	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34DRLRG4	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34YEAR	TI	获取价格	AUC SERIES, DUAL 1-INPUT NON-INVERT GATE, PBGA6, DSBGA-6
SN74AUC2G34YEPR	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34YZAR	TI	获取价格	AUC SERIES, DUAL 1-INPUT NON-INVERT GATE, PBGA6, DSBGA-6
SN74AUC2G34YZPR	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34YZTR	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera

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