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SN74AUC2G34DRLR PDF预览

SN74AUC2G34DRLR

更新时间： 2024-11-16 05:17:39
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路光电二极管
页数 文件大小 规格书
13页 529K
描述
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation

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SN74AUC2G34DRLR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOT
包装说明：SOT-553, 6 PIN针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.5Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：753873
Samacsys Pin Count：6Samacsys Part Category：Integrated Circuit
Samacsys Package Category：SOT23 (6-Pin)Samacsys Footprint Name：SOT-5X3
Samacsys Released Date：2019-03-18 13:40:12Is Samacsys：N
系列：AUCJESD-30 代码：R-PDSO-F6
JESD-609代码：e4长度：1.6 mm
负载电容（CL）：15 pF逻辑集成电路类型：BUFFER
最大I（ol）：0.009 A湿度敏感等级：1
功能数量：2输入次数：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VSOF
封装等效代码：TSSOP6,.06,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：1.2/2.5 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：3.4 ns
传播延迟（tpd）：3.4 ns认证状态：Not Qualified
施密特触发器：NO座面最大高度：0.6 mm
子类别：Gates最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：FLAT端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.2 mmBase Number Matches：1

SN74AUC2G34DRLR 数据手册

 浏览型号SN74AUC2G34DRLR的Datasheet PDF文件第2页浏览型号SN74AUC2G34DRLR的Datasheet PDF文件第3页浏览型号SN74AUC2G34DRLR的Datasheet PDF文件第4页浏览型号SN74AUC2G34DRLR的Datasheet PDF文件第5页浏览型号SN74AUC2G34DRLR的Datasheet PDF文件第6页浏览型号SN74AUC2G34DRLR的Datasheet PDF文件第7页 
SN74AUC2G34  
DUAL BUFFER GATE  
www.ti.com  
SCES514A–NOVEMBER 2003–REVISED MARCH 2006  
FEATURES  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
±8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
– 1000-V Charged-Device Model (C101)  
•
•
•
Sub-1-V Operable  
Max tpd of 1.6 ns at 1.8 V  
Low Power Consumption, 10 µA at 1.8 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
YEP PACKAGE  
(BOTTOM VIEW)  
1Y  
VCC  
2Y  
1
2
3
6
5
4
1A  
GND  
2A  
1
2
3
6
5
4
1A  
GND  
2A  
1Y  
VCC  
2Y  
1
2
3
6
5
4
1A  
GND  
2A  
1Y  
VCC  
2Y  
3
2
1
4
5
6
2Y  
VCC  
1Y  
2A  
GND  
1A  
DESCRIPTION/ORDERING INFORMATION  
This dual buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC  
operation.  
The SN74AUC2G34 performs the Boolean function Y = A in positive logic.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74AUC2G34YEPR  
_ _ _U9_  
Tape and reel  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AUC2G34YZPR  
–40°C to 85°C  
SOT-563 – DRL  
SOT-23 – DBV  
SC-70 – DCK  
Tape and reel  
Tape and reel  
Tape and reel  
SN74AUC2G34DRLR  
SN74AUC2G34DBVR  
SN74AUC2G34DCKR  
U9_  
U34_  
U9_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...13

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SN74AUC2G34DRLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC2G34DRLRG4 TI

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 Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera

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SN74AUC2G34YEAR TI

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 		AUC SERIES, DUAL 1-INPUT NON-INVERT GATE, PBGA6, DSBGA-6
SN74AUC2G34YEPR TI

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SN74AUC2G34YZAR TI

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 		AUC SERIES, DUAL 1-INPUT NON-INVERT GATE, PBGA6, DSBGA-6
SN74AUC2G34YZPR TI

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 		Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34YZTR TI

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 		SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER
SN74AUC2G53_07 TI

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SN74AUC2G53_09 TI

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 		SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER
SN74AUC2G53DCTR TI

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 		SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

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