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SN74AUC2G34YEAR PDF预览

SN74AUC2G34YEAR

更新时间： 2024-11-16 19:00:07
品牌 Logo 应用领域
德州仪器 - TI 栅输入元件逻辑集成电路触发器
页数 文件大小 规格书
13页 322K
描述
AUC SERIES, DUAL 1-INPUT NON-INVERT GATE, PBGA6, DSBGA-6

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SN74AUC2G34YEAR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA, BGA6,2X3,20
针数：6Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.61
系列：AUCJESD-30 代码：R-PBGA-B6
长度：1.4 mm负载电容（CL）：15 pF
逻辑集成电路类型：BUFFER最大I（ol）：0.005 A
功能数量：2输入次数：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA6,2X3,20
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.2/2.5 VProp。Delay @ Nom-Sup：3.4 ns
传播延迟（tpd）：3.4 ns认证状态：Not Qualified
施密特触发器：NO座面最大高度：0.5 mm
子类别：Gates最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.9 mm
Base Number Matches：1

SN74AUC2G34YEAR 数据手册

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SCES514 − NOVEMBER 2003  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1A  
GND  
2A  
1Y  
V
2Y  
1
2
3
6
5
4
CC  
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
D
D
D
D
D
Sub 1-V Operable  
Max t of 1.6 ns at 1.8 V  
pd  
Low Power Consumption, 10 µA at 1.8 V  
3 4  
2 5  
1 6  
2A  
GND  
1A  
2Y  
V
CC  
8-mA Output Drive at 1.8 V  
1Y  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This dual buffer gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V V  
CC  
operation.  
CC  
The SN74AUC2G34 performs the Boolean function Y = A in positive logic.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74AUC2G34YEPR  
Tape and reel  
_ _ _U9_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SN74AUC2G34YZPR  
−40°C to 85°C  
SOT (SOT-23) − DBV  
Tape and reel SN74AUC2G34DBVR  
Tape and reel SN74AUC2G34DCKR  
U34_  
U9_  
SOT (SC-70) − DCK  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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