Datasheet > SN74AUC2G32_09

SN74AUC2G32_09

更新时间： 2024-09-28 11:53:19

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
13页	528K
描述
DUAL 2-INPUT POSITIVE-OR GATE

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SN74AUC2G32_09 数据手册

SN74AUC2G32

DUAL 2-INPUT POSITIVE-OR GATE

www.ti.com

SCES478C–AUGUST 2003–REVISED JANUARY 2007

FEATURES

•

Available in the Texas Instruments

NanoFree™ Package

•

Low Power Consumption, 10 µA at 1.8 V

±8-mA Output Drive at 1.8 V

•

Optimized for 1.8-V Operation and is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

•

I_offSupports Partial-Power-Down Mode

Operation

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

•

Sub-1-V Operable

1000-V Charged-Device Model (C101)

Max t_pdof 1.5 ns at 1.8 V

YZP PACKAGE

(BOTTOM VIEW)

DCT PACKAGE

(TOP VIEW)

DCU PACKAGE

(TOP VIEW)

4 5

GND

V_CC

3 6

2 7

1 8

V_CC

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

This dual 2-input positive-OR gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to

1.95-V V_CCoperation.

The SN74AUC2G32 performs the Boolean function Y = A + B or Y = A × B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, please refer to the TI application report, Applications of

Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

NanoFree – WCSP (DSBGA)

ORDERABLE PART NUMBER

TOP-SIDE MARKING⁽²⁾

0.23-mm Large Bump – YZP

(Pb-free)

Reel of 3000

SN74AUC2G32YZPR

_ _ _UG_

–40°C to 85°C

SSOP – DCT

Reel of 3000

SN74AUC2G32DCTR

SN74AUC2G32DCUR

U32_ _ _

U32_

VSSOP – DCU

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...13

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与SN74AUC2G32_09相关器件

型号	品牌	获取价格	描述	数据表
SN74AUC2G32DCTR	TI	获取价格	DUAL 2 INPUT POSITIVE OR GATE
SN74AUC2G32DCTRE4	TI	获取价格	DUAL 2-INPUT POSITIVE-OR GATE
SN74AUC2G32DCUR	TI	获取价格	DUAL 2 INPUT POSITIVE OR GATE
SN74AUC2G32DCURE4	TI	获取价格	DUAL 2-INPUT POSITIVE-OR GATE
SN74AUC2G32DCURG4	TI	获取价格	DUAL 2-INPUT POSITIVE-OR GATE
SN74AUC2G32YEPR	TI	获取价格	DUAL 2 INPUT POSITIVE OR GATE
SN74AUC2G32YZPR	TI	获取价格	DUAL 2 INPUT POSITIVE OR GATE
SN74AUC2G32YZTR	TI	获取价格	AUC SERIES, DUAL 2-INPUT OR GATE, PBGA8, ROHS COMPLIANT, DSBGA-8
SN74AUC2G34	TI	获取价格	Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Opera
SN74AUC2G34_09	TI	获取价格	DUAL BUFFER GATE

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