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PI74SSTV16859ZB PDF预览

PI74SSTV16859ZB

更新时间： 2024-11-04 23:27:51
品牌 Logo 应用领域
其他 - ETC 驱动器存储逻辑集成电路电视
页数 文件大小 规格书
7页 214K
描述
Memory Driver

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PI74SSTV16859ZB 数据手册

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PI74SSTV16859  
13-Bit to 26-Bit Registered Buffer  
ProductFeatures  
ProductDescription  
• PI74SSTV16859isdesignedforlow-voltageoperation,  
PericomSemiconductor’sPI74SSTV16859logiccircuitisproduced  
using the Company’s advanced 0.35 micron CMOS technology,  
achieving industry leading speed.  
V
DD  
=V  
= 2.3V to 2.7V  
DDQ  
• Supports SSTL_2 Class II specifications on outputs  
• AllInputsareSSTL_2Compatible,exceptRESET  
whichisLVCMOS.  
• Designed for DDR Memory  
• Flow-Through Architecture  
• Packages:  
All inputs are compatible with the JEDEC standard for SSTL_2,  
excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,  
ClassIIcompatible.  
Thedeviceoperatesfromadifferentialclock(CLKandCLK). Data  
registeredatthecrossingofCLKgoingHIGH,andCLKgoingLOW.  
64-pin,240-milwideplasticTSSOP(A)  
56-pin, Plastic Very Thin Fine Pitch Quad Flat  
No Lead QFN (ZB)  
ThePI74SSTV16859supportslow-powerstandbyoperation.When  
RESET is LOW, the differential input receivers are disabled, and  
undriven (floating) data, clock and reference voltage (VREF) inputs  
areallowed.Inaddition,whenRESETisLOW,allregistersarereset,  
and all outputs are forced LOW. The LVCMOS RESET input must  
always be held at a valid logic HIGH or LOW level.  
Logic Block Diagram - TSSOP  
48  
CLK  
49  
CLK  
To ensure defined outputs from the register before a stable clock  
has been supplied, RESET must be held in the LOW state during  
power up.  
16  
51  
Q1A  
Q1B  
RESET  
R
CLK  
35  
45  
32  
D1  
IntheDDRDIMMapplication,RESETisspecifiedtobecompletely  
asynchronous with respect to CLK and CLK. Therefore, no timing  
relationship can be guaranteed between the two. When entering  
RESET, the register will be cleared and the outputs will be driven  
LOW quickly, relative to the time to disable the differential input  
receivers, thus ensuring no glitches on the output. However, when  
comingoutof RESET,theregisterwillbecomeactivequickly,relative  
to the time to enable the differential input receivers. When the data  
inputs are LOW, and the clock is stable, during the time from the  
LOW-to-HIGH transition of RESET until the input receivers  
are fully enabled, the design must ensure that the outputs will  
remainLOW.  
D
V
REF  
TO 12 OTHER CHANNELS  
Logic Block Diagram - QFN  
35  
CLK  
36  
CLK  
7
38  
Q1A  
Q1B  
RESET  
R
D
CLK  
24  
D1  
22  
32  
V
Pericom’s PI74SSTV16859 is characterized for operation from  
0°Cto70°C.  
REF  
TruthTable(1)  
TO 12 OTHER CHANNELS  
Inputs  
Outputs  
Q
ProductPinDescription  
RESET  
CLK  
CLK  
D
Pin Name  
RESET  
CLK  
CLK  
D
Description  
X or  
X or  
X or  
Floating  
L
L
Reset (Active Low) LVCMOS  
Floating  
Floating  
Clock Input, Positive Differential Input  
H
Η
H
↑
↑
↓
↓
H
L
H
L
Qo(2)  
Clock Input, Negative Differential Input  
Data Input, D1-D13  
L or H  
L or H  
X
Q
Data Output, Q1-Q13  
Notes:  
GND  
VDD  
Ground  
1.  
H
L
↑
↓
X
= HighSignalLevel  
= LowSignalLevel  
= Transition LOW-to-HIGH  
= Transition HIGH-to-LOW  
= Irrelevant or floating  
2. Output level before the  
indicated steady state  
input conditions were  
established.  
Core Supply Voltage, 2.5V Nominal  
Output Supply Voltage, 2.5V Nominal  
Input Reference Voltage, 1.25V Nominal  
VDDQ  
VREF  
1
PS8508A  
08/30/01  
1234567

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