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PI74SSTVF16857A PDF预览

PI74SSTVF16857A

更新时间: 2024-11-05 10:12:55
品牌 Logo 应用领域
百利通 - PERICOM 触发器锁存器逻辑集成电路电视光电二极管
页数 文件大小 规格书
8页 186K
描述
14-Bit Registered Buffer

PI74SSTVF16857A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:0.240 INCH, PLASTIC, TSSOP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.18Is Samacsys:N
系列:SSTVJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
逻辑集成电路类型:D FLIP-FLOP位数:14
功能数量:1端子数量:48
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5 V
传播延迟(tpd):2.2 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Logic ICs
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
最小 fmax:210 MHzBase Number Matches:1

PI74SSTVF16857A 数据手册

 浏览型号PI74SSTVF16857A的Datasheet PDF文件第2页浏览型号PI74SSTVF16857A的Datasheet PDF文件第3页浏览型号PI74SSTVF16857A的Datasheet PDF文件第4页浏览型号PI74SSTVF16857A的Datasheet PDF文件第5页浏览型号PI74SSTVF16857A的Datasheet PDF文件第6页浏览型号PI74SSTVF16857A的Datasheet PDF文件第7页 
PI74SSTVF16857A  
14-Bit Registered Buffer  
ProductFeatures  
ProductDescription  
• Designed for low-voltage operation,  
2.5VforPC1600~PC2700;2.6VforPC3200  
• Supports SSTL_2 Class I output specifications  
• SSTL_2 Input and Output Levels  
PericomSemiconductor’sPI74SSTVF16857A seriesoflogiccircuits  
are produced using the Company’s advanced sub-micron CMOS  
technology, achieving industry leading speed.  
The 14-bit PI74SSTVF16857A universal bus driver is designed  
• Designed for DDR Memory  
• Flow-Through Architecture  
• Packaging Options (Lead-free packages are available):  
48-pin240milwideplasticTSSOP(A)  
48-pin173milwideplasticTVSOP(K)  
for2.5Vto2.6VV operation and SSTL_2 I/O Levels except for  
DD  
theRESETinputwhichisLVCMOS.  
Data flowfrom DtoQiscontrolledbythe differential clock, CLK,  
CLK and RESET. Data is triggered on the positive edge of CLK.  
CLK must be used to maintain noise margins.  
RESET must be supported with LVCMOS levels as V  
may not  
REF  
LogicBlockDiagram  
bestableduringpower-up.RESETisasynchronousandisintended  
forpower-uponlyandwhenlowassuresthatalloftheregistersreset  
totheLowState,Qoutputsarelow,andallinputreceivers,dataand  
clock, are switched off.  
38  
CLK  
39  
CLK  
34  
RESET  
R
Pericom’sPI74SSTVF16857Aischaracterizedforoperationfrom  
0°to70°C.  
1
CLK  
Q1  
48  
35  
D1  
D
V
REF  
ProductPinConfiguration  
TO 13 OTHER CHANNELS  
Q1  
Q2  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
D1  
ProductPinDescription  
2
D2  
PinName  
RESET  
CLK  
CLK  
D
Description  
GND  
3
GND  
Reset (Active Low)  
Clock Input  
Clock Input  
V
4
V
DDQ  
Q3  
DD  
5
D3  
Q4  
Q5  
6
D4  
7
D5  
Data Input  
GND  
8
D6  
Q
Data Output  
V
V
9
D7  
DDQ  
Q6  
GND  
Ground  
48-Pin  
A,K  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CLK  
CLK  
V
Core Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
DD  
Q7  
V
V
DDQ  
V
DDQ  
GND  
DD  
REF  
GND  
TruthTable(1)  
Q8  
Q9  
V
REF  
RESET  
D8  
Inputs  
Outputs  
V
V
DDQ  
GND  
RESET  
CLK  
CLK  
D
X
H
L
Q
L
H
L
Qo(2)  
D9  
L
H
X
X
Q10  
Q11  
Q12  
D10  
D11  
D12  
Η
V
H
L or H  
L or H  
X
DDQ  
GND  
DD  
GND  
D13  
D14  
Notes:  
2. Output level before the  
indicated steady state  
input conditions were  
established.  
1. H = HighSignalLevel  
L = LowSignalLevel  
Q13  
Q14  
= TransitionLOW-to-HIGH  
=TransitionHIGH-to-LOW  
X = Irrelevant  
PS8687  
05/27/03  
1

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