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PI74SSTVF16859AZB

更新时间： 2024-09-13 13:12:19
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
8页 192K
描述
D Flip-Flop, SSTV Series, 1-Func, 13-Bit, True Output, CMOS, PQCC56, PLASTIC, MO-220VLLD-2, QFN-56

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PI74SSTVF16859AZB 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFN包装说明：HVQCCN, LCC56,.31SQ,20
针数：56Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.26Is Samacsys：N
系列：SSTVJESD-30 代码：S-PQCC-N56
JESD-609代码：e0长度：8 mm
逻辑集成电路类型：D FLIP-FLOP位数：13
功能数量：1端子数量：56
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC56,.31SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
传播延迟（tpd）：1.8 ns认证状态：Not Qualified
座面最大高度：0.84 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm
最小 fmax：210 MHzBase Number Matches：1

PI74SSTVF16859AZB 数据手册

 浏览型号PI74SSTVF16859AZB的Datasheet PDF文件第2页浏览型号PI74SSTVF16859AZB的Datasheet PDF文件第3页浏览型号PI74SSTVF16859AZB的Datasheet PDF文件第4页浏览型号PI74SSTVF16859AZB的Datasheet PDF文件第5页浏览型号PI74SSTVF16859AZB的Datasheet PDF文件第6页浏览型号PI74SSTVF16859AZB的Datasheet PDF文件第7页 
PI74SSTVF16859  
13-Bit to 26-Bit Registered Buffer  
ProductDescription  
ProductFeatures  
• PI74SSTVF16859isdesignedforlow-voltageoperation,  
2.5VforPC1600~PC2700;2.6VforPC3200  
• Supports SSTL_2 Class I specifications on outputs  
• All InputsareSSTL_2Compatible,exceptRESET  
whichisLVCMOS.  
PericomSemiconductor’sPI74SSTVF16859logiccircuitisproduced  
using the Company’s advanced sub-micron CMOS technology,  
achieving industry leading speed.  
All inputs are compatible with the JEDEC standard for SSTL_2,  
excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,  
ClassIIcompatible.  
• Designed for DDR Memory  
• Flow-Through Architecture  
• Packages:  
Thedeviceoperatesfromadifferentialclock(CLKandCLK).Data  
registeredatthecrossingofCLKgoingHIGH,andCLKgoingLOW.  
64-pin,240-milwideplasticTSSOP(A)  
56-pin, Plastic Very Thin Fine Pitch Quad Flat  
No Lead QFN (ZB)  
ThePI74SSTVF16859supportslow-powerstandbyoperation.When  
RESET is LOW, the differential input receivers are disabled, and  
undriven (floating) data, clock and reference voltage (VREF) inputs  
areallowed.Inaddition,whenRESETisLOW,allregistersarereset,  
and all outputs are forced LOW. The LVCMOS RESET input must  
always be held at a valid logic HIGH or LOW level.  
To ensure defined outputs from the register before a stable clock  
has been supplied, RESET must be held in the LOW state during  
power up.  
IntheDDRDIMMapplication,RESETisspecifiedtobecompletely  
asynchronous with respect to CLK and CLK. Therefore, no timing  
relationship can be guaranteed between the two. When entering  
RESET, the register will be cleared and the outputs will be driven  
LOW quickly, relative to the time to disable the differential input  
receivers, thus ensuring no glitches on the output. However, when  
comingoutof RESET,theregisterwillbecomeactivequickly,relative  
to the time to enable the differential input receivers. When the data  
inputs are LOW, and the clock is stable, during the time from the  
LOW-to-HIGH transition of RESET until the input receivers  
are fully enabled, the design must ensure that the outputs will  
remainLOW.  
Logic Block Diagram - TSSOP  
48  
CLK  
49  
CLK  
16  
51  
Q1A  
RESET  
R
D
CLK  
35  
45  
32  
D1  
Q1B  
V
REF  
TO 12 OTHER CHANNELS  
Logic Block Diagram - QFN  
35  
CLK  
36  
CLK  
7
38  
Q1A  
Q1B  
RESET  
R
D
CLK  
24  
D1  
22  
Pericom’s PI74SSTVF16859 is characterized for operation from  
0°Cto70°C.  
32  
V
REF  
TO 12 OTHER CHANNELS  
TruthTable(1)  
ProductPinDescription  
Inputs  
Outputs  
Q
Pin Name  
Description  
Reset (Active Low) LVCMOS  
Clock Input, Positive Differential Input  
Clock Input, Negative Differential Input  
Data Input, D1-D13  
Data Output, Q1-Q13  
Ground  
RESET  
CLK  
CLK  
X or  
D
RESET  
CLK  
CLK  
D
X or  
X or  
Floating  
L
L
Floating  
Floating  
H
Η
H
↑
↓
H
L
X
H
L
Qo(2)  
↑
↓
Q
L or H  
L or H  
GND  
VDD  
VDDQ  
VREF  
Notes:  
1.  
H
L
↑
= HighSignalLevel  
= LowSignalLevel  
2. Output level before the  
indicated steady state  
input conditions were  
established.  
Core Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
= Transition LOW-to-HIGH  
= Transition HIGH-to-LOW  
= Irrelevant or floating  
↓
X
1
PS8657  
02/13/03  
12345678

中文翻译

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与PI74SSTVF16859AZB相关器件

型号 品牌 获取价格 描述 数据表
PI74SSTVF16859AZBE PERICOM

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 		D Flip-Flop, SSTV Series, 1-Func, 13-Bit, True Output, CMOS, PQCC56, LEAD FREE, PLASTIC, M
PI74SSTVF16859AZBEX PERICOM

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 		D Flip-Flop, SSTV Series, 1-Func, 13-Bit, True Output, CMOS, PQCC56, LEAD FREE, PLASTIC, M
PI74SSTVF16859AZBX PERICOM

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 		D Flip-Flop, SSTV Series, 1-Func, 13-Bit, True Output, CMOS, PQCC56, PLASTIC, MO-220VLLD-2
PI74SSTVF16859ZB PERICOM

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 		13-Bit to 26-Bit Registered Buffer
PI74SSTVF16859ZBE PERICOM

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 		暂无描述
PI74SSTVF32852 ETC

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 		Logic | DDR-I. 24/48-Bit Registered Buffer - LFBGA Package
PI74SSTVF32852ANB PERICOM

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 		D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LFBGA-114
PI74SSTVF32852ANBE PERICOM

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 		D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LEAD FREE, LFBGA-114
PI74SSTVF32852NB PERICOM

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 		D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, CMOS, PBGA
PI74SSTVF32852NBEX PERICOM

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 		Bus Driver, CMOS, PBGA114

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