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PI74SSTVF16859AZBEX PDF预览

PI74SSTVF16859AZBEX

更新时间： 2024-09-13 19:22:23
品牌 Logo 应用领域
百利通 - PERICOM 逻辑集成电路电视
页数 文件大小 规格书
8页 249K
描述
D Flip-Flop, SSTV Series, 1-Func, 13-Bit, True Output, CMOS, PQCC56, LEAD FREE, PLASTIC, MO-220VLLD-2, QFN-56

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中文翻译

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PI74SSTVF16859AZBEX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：HVQCCN, LCC56,.31SQ,20
针数：56Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.26系列：SSTV
JESD-30 代码：S-PQCC-N56JESD-609代码：e3
长度：8 mm逻辑集成电路类型：D FLIP-FLOP
湿度敏感等级：1位数：13
功能数量：1端子数量：56
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC56,.31SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：2.5 V
传播延迟（tpd）：1.8 ns认证状态：Not Qualified
座面最大高度：0.84 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：8 mm
最小 fmax：210 MHzBase Number Matches：1

PI74SSTVF16859AZBEX 数据手册

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PI74SSTVF16859A  
13-Bit to 26-Bit Registered Buffer  
ProductFeatures  
ProductDescription  
• PI74SSTVF16859Aisdesignedforlow-voltageoperation,  
2.5VforPC1600~PC2700;2.6VforPC3200  
Pericom Semiconductor’s PI74SSTVF16859A logic circuit is  
produced using the Company’s advanced sub-micron CMOS  
technology, achieving industry leading speed.  
• Supports SSTL_2 Class I specifications on outputs  
All inputs are compatible with the JEDEC standard for SSTL_2,  
excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,  
ClassIIcompatible.  
• All InputsareSSTL_2Compatible,exceptRESET  
whichisLVCMOS.  
• Designed for DDR Memory  
• Flow-Through Architecture  
Thedeviceoperatesfromadifferentialclock(CLKandCLK).Data  
registeredatthecrossingofCLKgoingHIGH,andCLKgoingLOW.  
• Package: 56-pin, Plastic Very Thin Fine Pitch Quad Flat No-  
LeadQFN(ZB).(Pb-freeavailable)  
The PI74SSTVF16859A supports low-power standby operation.  
WhenRESETisLOW, thedifferentialinputreceiversaredisabled,  
and undriven (floating) data, clock and reference voltage (VREF  
)
inputsareallowed.Inaddition,whenRESETisLOW,allregistersare  
reset, andalloutputsareforcedLOW. TheLVCMOSRESETinput  
must always be held at a valid logic HIGH or LOW level.  
LogicBlockDiagram  
35  
CLK  
36  
To ensure defined outputs from the register before a stable clock  
has been supplied, RESET must be held in the LOW state during  
power up.  
CLK  
7
38  
Q1A  
Q1B  
RESET  
R
D
CLK  
24  
32  
22  
D1  
IntheDDRDIMMapplication,RESETisspecifiedtobecompletely  
asynchronous with respect to CLK and CLK. Therefore, no timing  
relationship can be guaranteed between the two. When entering  
RESET, the register will be cleared and the outputs will be driven  
LOW quickly, relative to the time to disable the differential input  
receivers, thus ensuring no glitches on the output. However, when  
comingoutof RESET,theregisterwillbecomeactivequickly,relative  
to the time to enable the differential input receivers. When the data  
inputs are LOW, and the clock is stable, during the time from the  
LOW-to-HIGH transition of RESET until the input receivers  
are fully enabled, the design must ensure that the outputs will  
remainLOW.  
V
REF  
TO 12 OTHER CHANNELS  
TruthTable(1)  
Inputs  
Outputs  
Q
RESET  
CLK  
X or  
Floating  
CLK  
D
X or  
Floating  
X or  
Floating  
L
L
Pericom’s PI74SSTVF16859A is characterized for operation from  
0°Cto70°C.  
H
Η
H
↑
↑
↓
↓
H
L
H
L
Qo(2)  
ProductPinDescription  
L or H  
L or H  
X
Notes:  
Pin Name  
RESET  
CLK  
CLK  
D
Description  
Reset (Active Low) LVCMOS  
Clock Input, Positive Differential Input  
Clock Input, Negative Differential Input  
Data Input, D1-D13  
1.  
H
L
↑
↓
X
= HighSignalLevel  
= LowSignalLevel  
= Transition LOW-to-HIGH  
= Transition HIGH-to-LOW  
= Irrelevant or floating  
2. Output level before the  
indicated steady state  
input conditions were  
established.  
Q
Data Output, Q1-Q13  
GND  
VDD  
Ground  
Core Supply Voltage  
VDDQ  
VREF  
Output Supply Voltage  
Input Reference Voltage  
1
PS8684B  
10/30/06  
06-0288  
12345678

中文翻译

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