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PI74SSTVF32852ANB PDF预览

PI74SSTVF32852ANB

更新时间： 2024-09-13 19:45:31
品牌 Logo 应用领域
百利通 - PERICOM 逻辑集成电路电视
页数 文件大小 规格书
8页 193K
描述
D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LFBGA-114

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中文翻译

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PI74SSTVF32852ANB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA, BGA114,6X19,32针数：114
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.27
系列：SSTVJESD-30 代码：R-PBGA-B114
JESD-609代码：e0长度：16 mm
逻辑集成电路类型：D FLIP-FLOP湿度敏感等级：3
位数：24功能数量：1
端子数量：114最高工作温度：70 °C
最低工作温度：输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA114,6X19,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：240
电源：2.5 V传播延迟（tpd）：2.1 ns
认证状态：Not Qualified座面最大高度：1.45 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.5 mm最小 fmax：210 MHz
Base Number Matches：1

PI74SSTVF32852ANB 数据手册

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PI74SSTVF32852A  
24-Bit to 48-Bit Registered Buffer  
ProductFeatures  
ProductDescription  
Pericom Semiconductor’s PI74SSTVF32852A logic circuit is  
produced using the Company’s advanced sub-micron CMOS  
technology, achieving industry leading speed.  
All inputs are compatible with the JEDEC standard for SSTL_2,  
excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,  
ClassIIcompatible.  
The device operates from a differential clock (CK and CK). Data  
registered at the crossing of CK going HIGH, and CK going LOW.  
• PI74SSTVF32852Aisdesignedforlow-voltageoperation,  
2.5VforPC1600~PC2700;2.6VforPC3200  
• Supports SSTL_2 Class I specifications on outputs  
• AllInputsareSSTL_2Compatible,exceptRESET  
whichisLVCMOS.  
• Designed for DDR Memory  
• Packaging:114-BallLFBGA  
•Pb-freeavailable  
The PI74SSTVF32852A supports low-power standby operation.  
WhenRESETisLOW, thedifferentialinputreceiversaredisabled,  
and undriven (floating) data, clock and reference voltage (VREF)  
inputs are allowed. In addition, when RESET is LOW, all registers  
are reset, and all outputs are forced LOW. The LVCMOS RESET  
input must always be held at a valid logic HIGH or LOW level.  
To ensure defined outputs from the register before a stable clock  
has been supplied, RESET must be held in the LOW state during  
power up.  
LogicBlockDiagram  
A3  
CLK  
A4  
CLK  
A2  
R3  
Q1A  
Q1B  
RESET  
R
D
CLK  
T2  
R4  
A5  
D1  
V
REF  
IntheDDRDIMMapplication,RESETisspecifiedtobecompletely  
asynchronous with respect to CK and CK. Therefore, no timing  
relationship can be guaranteed between the two. When entering  
RESET, the register will be cleared and the outputs will be driven  
LOW quickly, relative to the time to disable the differential input  
receivers, thus ensuring no glitches on the output. However, when  
comingoutof RESET,theregisterwillbecomeactivequickly,relative  
to the time to enable the differential input receivers. When the data  
inputs are LOW, and the clock is stable, during the time from the  
LOW-to-HIGH transition of RESET until the input receivers  
are fully enabled, the design must ensure that the outputs will  
remainLOW.  
TO 23 OTHER CHANNELS  
ProductPinDescription  
Pin Name  
Description  
Reset (Active Low) LVCMOS  
Clock Input, Positive Differential Input  
Clock Input, Negative Differential Input  
Data Input  
RESET  
CLK  
CLK  
D
Q
Data Output  
GND  
VDD  
VDDQ  
VREF  
Ground  
Pericom’s PI74SSTVF32852A is characterized for operation from  
0°to70°C.  
Core Supply Voltage, 2.5V Nominal  
Output Supply Voltage, 2.5V Nominal  
Input Reference Voltage, 1.25V Nominal  
TruthTable(1)  
Inputs  
Outputs  
RESET  
CLK  
X or Floating  
CLK  
X or Floating  
D
Q
L
L
X or Floating  
H
Η
↑
↓
H
L
H
L
↑
↓
H
L or H  
L or H  
X
Qo(2)  
Notes:  
1. H= High Signal Level; L = Low Signal Level; ↑ = Transition LOW-to-HIGH; ↓ = Transition HIGH-to-LOW  
X = Irrelevant or floating  
2. Output level before the indicated steady state input conditions were established.  
1
PS8682  
04/07/03  
12345678

中文翻译

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