PI74SSTVF16859
13-Bit to 26-Bit Registered Buffer
ProductDescription
ProductFeatures
• PI74SSTVF16859isdesignedforlow-voltageoperation,
2.5VforPC1600~PC2700;2.6VforPC3200
• Supports SSTL_2 Class I specifications on outputs
• All InputsareSSTL_2Compatible,exceptRESET
whichisLVCMOS.
PericomSemiconductor’sPI74SSTVF16859logiccircuitisproduced
using the Company’s advanced sub-micron CMOS technology,
achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,
ClassIIcompatible.
• Designed for DDR Memory
• Flow-Through Architecture
• Packages:
Thedeviceoperatesfromadifferentialclock(CLKandCLK).Data
registeredatthecrossingofCLKgoingHIGH,andCLKgoingLOW.
64-pin,240-milwideplasticTSSOP(A)
56-pin, Plastic Very Thin Fine Pitch Quad Flat
No Lead QFN (ZB)
ThePI74SSTVF16859supportslow-powerstandbyoperation.When
RESET is LOW, the differential input receivers are disabled, and
undriven (floating) data, clock and reference voltage (VREF) inputs
areallowed.Inaddition,whenRESETisLOW,allregistersarereset,
and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
IntheDDRDIMMapplication,RESETisspecifiedtobecompletely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
comingoutof RESET,theregisterwillbecomeactivequickly,relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remainLOW.
Logic Block Diagram - TSSOP
48
CLK
49
CLK
16
51
Q1A
RESET
R
D
CLK
35
45
32
D1
Q1B
V
REF
TO 12 OTHER CHANNELS
Logic Block Diagram - QFN
35
CLK
36
CLK
7
38
Q1A
Q1B
RESET
R
D
CLK
24
D1
22
Pericom’s PI74SSTVF16859 is characterized for operation from
0°Cto70°C.
32
V
REF
TO 12 OTHER CHANNELS
TruthTable(1)
ProductPinDescription
Inputs
Outputs
Q
Pin Name
Description
Reset (Active Low) LVCMOS
Clock Input, Positive Differential Input
Clock Input, Negative Differential Input
Data Input, D1-D13
Data Output, Q1-Q13
Ground
RESET
CLK
CLK
X or
D
RESET
CLK
CLK
D
X or
X or
Floating
L
L
Floating
Floating
H
Η
H
↑
↓
H
L
X
H
L
Qo(2)
↑
↓
Q
L or H
L or H
GND
VDD
VDDQ
VREF
Notes:
1.
H
L
↑
= HighSignalLevel
= LowSignalLevel
2. Output level before the
indicated steady state
input conditions were
established.
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
= Transition LOW-to-HIGH
= Transition HIGH-to-LOW
= Irrelevant or floating
↓
X
1
PS8657
02/13/03