Datasheet > PI74SSTVF32852

PI74SSTVF32852

更新时间： 2024-09-12 23:27:51

品牌	Logo	应用领域
其他 - ETC		双倍数据速率
页数	文件大小	规格书
8页	193K
描述
Logic \| DDR-I. 24/48-Bit Registered Buffer - LFBGA Package

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PI74SSTVF32852 数据手册

PI74SSTVF32852

24-Bit to 48-Bit Registered Buffer

ProductFeatures

ProductDescription

PericomSemiconductor’sPI74SSTVF32852 logiccircuitisproduced

using the Company’s advanced sub-micron CMOS technology,

achieving industry leading speed.

All inputs are compatible with the JEDEC standard for SSTL_2,

excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,

ClassIIcompatible.

The device operates from a differential clock (CK and CK). Data

registered at the crossing of CK going HIGH, and CK going LOW.

• PI74SSTVF32852isdesignedforlow-voltageoperation,

2.5VforPC1600~PC2700;2.6VforPC3200

• Supports SSTL_2 Class I specifications on outputs

• AllInputsareSSTL_2Compatible,exceptRESET

whichisLVCMOS.

• Designed for DDR Memory

• Packaging: 114-BallLFBGA

(Lead-freepackageavailable)

The PI74SSTVF32852 supports low-power standby operation.

WhenRESETisLOW, thedifferentialinputreceiversaredisabled,

and undriven (floating) data, clock and reference voltage (VREF)

inputs are allowed. In addition, when RESET is LOW, all registers

are reset, and all outputs are forced LOW. The LVCMOS RESET

input must always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock

has been supplied, RESET must be held in the LOW state during

power up.

LogicBlockDiagram

CLK

Q1A

RESET

CLK

Q1B

REF

IntheDDRDIMMapplication,RESETisspecifiedtobecompletely

asynchronous with respect to CK and CK. Therefore, no timing

relationship can be guaranteed between the two. When entering

RESET, the register will be cleared and the outputs will be driven

LOW quickly, relative to the time to disable the differential input

receivers, thus ensuring no glitches on the output. However, when

comingoutof RESET,theregisterwillbecomeactivequickly,relative

to the time to enable the differential input receivers. When the data

inputs are LOW, and the clock is stable, during the time from the

LOW-to-HIGH transition of RESET until the input receivers

are fully enabled, the design must ensure that the outputs will

remainLOW.

TO 23 OTHER CHANNELS

ProductPinDescription

Pin Name

Description

Reset (Active Low) LVCMOS

Clock Input, Positive Differential Input

Clock Input, Negative Differential Input

Data Input

RESET

CLK

Data Output

GND

V_DD

V_DDQ

V_REF

Ground

Pericom’s PI74SSTVF32852 is characterized for operation from

0°to70°C.

Core Supply Voltage, 2.5V Nominal

Output Supply Voltage, 2.5V Nominal

Input Reference Voltage, 1.25V Nominal

TruthTable⁽¹⁾

Inputs

Outputs

RESET

CLK

X or Floating

CLK

X or Floating

↑

↓

↑

↓

L or H

Qo⁽²⁾

Notes:

1. H= High Signal Level; L = Low Signal Level; ↑ = Transition LOW-to-HIGH; ↓ = Transition HIGH-to-LOW

X = Irrelevant or floating

2. Output level before the indicated steady state input conditions were established.

PS8658A

04/08/03

12 3 4 5 6 7 8

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与PI74SSTVF32852相关器件

型号	品牌	获取价格	描述	数据表
PI74SSTVF32852ANB	PERICOM	获取价格	D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LFBGA-114
PI74SSTVF32852ANBE	PERICOM	获取价格	D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LEAD FREE, LFBGA-114
PI74SSTVF32852NB	PERICOM	获取价格	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 24-Bit, True Output, CMOS, PBGA
PI74SSTVF32852NBEX	PERICOM	获取价格	Bus Driver, CMOS, PBGA114
PI74SSTVF32852NBX	PERICOM	获取价格	Bus Driver, CMOS, PBGA114
PI74ST1G00	PERICOM	获取价格	SOTiny Logic 2-Input NAND Gate
PI74ST1G00CX	PERICOM	获取价格	SOTiny Logic 2-Input NAND Gate
PI74ST1G00TX	PERICOM	获取价格	SOTiny Logic 2-Input NAND Gate
PI74ST1G02	PERICOM	获取价格	SOTiny™ Logic 2-Input NOR Gate
PI74ST1G02CX	PERICOM	获取价格	SOTiny™ Logic 2-Input NOR Gate

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