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PI74SSTV32852NBE

更新时间： 2024-11-05 19:49:39
品牌 Logo 应用领域
百利通 - PERICOM 逻辑集成电路电视
页数 文件大小 规格书
7页 186K
描述
D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LEAD FREE, LFBGA-114

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PI74SSTV32852NBE 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA114,6X19,32
针数：114Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.27系列：SSTV
JESD-30 代码：R-PBGA-B114JESD-609代码：e1
长度：16 mm逻辑集成电路类型：D FLIP-FLOP
湿度敏感等级：3位数：24
功能数量：1端子数量：114
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA114,6X19,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：2.5 V
传播延迟（tpd）：3.3 ns认证状态：Not Qualified
座面最大高度：1.45 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：5.5 mm
最小 fmax：200 MHzBase Number Matches：1

PI74SSTV32852NBE 数据手册

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PI74SSTV32852  
24-Bit to 48-Bit Registered Buffer  
ProductFeatures  
ProductDescription  
PericomSemiconductor’sPI74SSTV32852logiccircuitisproduced  
using the Company’s advanced 0.35 micron CMOS technology,  
achieving industry leading speed.  
All inputs are compatible with the JEDEC standard for SSTL_2,  
excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,  
ClassIIcompatible.  
The device operates from a differential clock (CK and CK). Data  
registered at the crossing of CK going HIGH, and CK going LOW.  
ThePI74SSTV32852supportslow-powerstandbyoperation.When  
RESET is LOW, the differential input receivers are disabled, and  
undriven(floating)data,clockandreferencevoltage(VREF)inputs  
areallowed.Inaddition,whenRESETisLOW,allregistersarereset,  
and all outputs are forced LOW. The LVCMOS RESET input must  
always be held at a valid logic HIGH or LOW level.  
To ensure defined outputs from the register before a stable clock  
has been supplied, RESET must be held in the LOW state during  
power up.  
• PI74SSTV32852isdesignedforlow-voltageoperation,  
V
DD  
=V  
=2.3Vto2.7V  
DDQ  
• Supports SSTL_2 Class II specifications on outputs  
• AllInputsareSSTL_2Compatible,exceptRESET  
whichisLVCMOS.  
• Designed for DDR Memory  
• Packaging(Pb-freeavailable):  
114-BallLFBGA  
LogicBlockDiagram  
A3  
CLK  
A4  
CLK  
A2  
R3  
Q1A  
Q1B  
RESET  
R
CLK  
T2  
R4  
A5  
D1  
D
V
REF  
IntheDDRDIMMapplication,RESETisspecifiedtobecompletely  
asynchronous with respect to CK and CK. Therefore, no timing  
relationship can be guaranteed between the two. When entering  
RESET, the register will be cleared and the outputs will be driven  
LOW quickly, relative to the time to disable the differential input  
receivers, thus ensuring no glitches on the output. However, when  
comingoutof RESET,theregisterwillbecomeactivequickly,relative  
to the time to enable the differential input receivers. When the data  
inputs are LOW, and the clock is stable, during the time from the  
LOW-to-HIGH transition of RESET until the input receivers  
are fully enabled, the design must ensure that the outputs will  
remainLOW.  
TO 23 OTHER CHANNELS  
ProductPinDescription  
Pin Name  
Description  
Reset (Active Low) LVCMOS  
Clock Input, Positive Differential Input  
Clock Input, Negative Differential Input  
Data Input  
Data Output  
Ground  
Core Supply Voltage, 2.5V Nominal  
Output Supply Voltage, 2.5V Nominal  
Input Reference Voltage, 1.25V Nominal  
RESET  
CLK  
CLK  
D
Q
Pericom’s PI74SSTV32852 is characterized for operation from  
0°to70°C.  
GND  
VDD  
VDDQ  
VREF  
TruthTable(1)  
Inputs  
Outputs  
RESET  
CLK  
X or Floating  
CLK  
X or Floating  
D
Q
L
L
X or Floating  
H
Η
↑
↓
H
L
H
L
↑
↓
H
L or H  
L or H  
X
Qo(2)  
Notes:  
1. H = High Signal Level; L = Low Signal Level; ↑ = Transition LOW-to-HIGH; ↓ = Transition HIGH-to-LOW  
X = Irrelevant or floating  
2. Output level before the indicated steady state input conditions were established.  
1
PS8615A  
06/23/02  
1234567

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