Datasheet > PI74SSTV32852NB

PI74SSTV32852NB

更新时间： 2024-11-06 05:51:47

品牌	Logo	应用领域
百利通 - PERICOM		电视
页数	文件大小	规格书
7页	190K
描述
D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LFBGA-114

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中文翻译

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PI74SSTV32852NB 数据手册

PI74SSTV32852

24-Bit to 48-Bit Registered Buffer

ProductFeatures

ProductDescription

PericomSemiconductor’sPI74SSTV32852logiccircuitisproduced

using the Company’s advanced 0.35 micron CMOS technology,

achieving industry leading speed.

All inputs are compatible with the JEDEC standard for SSTL_2,

excepttheLVCMOSreset(RESET)input.AlloutputsareSSTL_2,

ClassIIcompatible.

The device operates from a differential clock (CK and CK). Data

registered at the crossing of CK going HIGH, and CK going LOW.

ThePI74SSTV32852supportslow-powerstandbyoperation.When

RESET is LOW, the differential input receivers are disabled, and

undriven(floating)data,clockandreferencevoltage(VREF)inputs

areallowed.Inaddition,whenRESETisLOW,allregistersarereset,

and all outputs are forced LOW. The LVCMOS RESET input must

always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock

has been supplied, RESET must be held in the LOW state during

power up.

• PI74SSTV32852isdesignedforlow-voltageoperation,

=2.3Vto2.7V

DDQ

• Supports SSTL_2 Class II specifications on outputs

• AllInputsareSSTL_2Compatible,exceptRESET

whichisLVCMOS.

• Designed for DDR Memory

• Packaging(Pb-freeavailable):

114-BallLFBGA

LogicBlockDiagram

CLK

Q1A

Q1B

RESET

CLK

REF

IntheDDRDIMMapplication,RESETisspecifiedtobecompletely

asynchronous with respect to CK and CK. Therefore, no timing

relationship can be guaranteed between the two. When entering

RESET, the register will be cleared and the outputs will be driven

LOW quickly, relative to the time to disable the differential input

receivers, thus ensuring no glitches on the output. However, when

comingoutof RESET,theregisterwillbecomeactivequickly,relative

to the time to enable the differential input receivers. When the data

inputs are LOW, and the clock is stable, during the time from the

LOW-to-HIGH transition of RESET until the input receivers

are fully enabled, the design must ensure that the outputs will

remainLOW.

TO 23 OTHER CHANNELS

ProductPinDescription

Pin Name

Description

Reset (Active Low) LVCMOS

Clock Input, Positive Differential Input

Clock Input, Negative Differential Input

Data Input

Data Output

Ground

Core Supply Voltage, 2.5V Nominal

Output Supply Voltage, 2.5V Nominal

Input Reference Voltage, 1.25V Nominal

RESET

CLK

Pericom’s PI74SSTV32852 is characterized for operation from

0°to70°C.

GND

V_DD

V_DDQ

V_REF

TruthTable⁽¹⁾

Inputs

Outputs

RESET

CLK

X or Floating

CLK

X or Floating

↑

↓

↑

↓

L or H

Qo⁽²⁾

Notes:

1. H = High Signal Level; L = Low Signal Level; ↑ = Transition LOW-to-HIGH; ↓ = Transition HIGH-to-LOW

X = Irrelevant or floating

2. Output level before the indicated steady state input conditions were established.

PS8615A

06/23/02

12 3 4 5 6 7

中文翻译

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与PI74SSTV32852NB相关器件

型号	品牌	获取价格	描述	数据表
PI74SSTV32852NBE	PERICOM	获取价格	D Flip-Flop, SSTV Series, 1-Func, 24-Bit, True Output, CMOS, PBGA114, LEAD FREE, LFBGA-114
PI74SSTV32852NBEX	PERICOM	获取价格	Bus Driver, CMOS, PBGA114
PI74SSTV32852NBX	PERICOM	获取价格	Bus Driver, CMOS, PBGA114,
PI74SSTVF16857	ETC	获取价格	Logic \| DDR-I. 14-Bit Registered Buffer
PI74SSTVF16857A	PERICOM	获取价格	14-Bit Registered Buffer
PI74SSTVF16857AA	PERICOM	获取价格	14-Bit Registered Buffer
PI74SSTVF16857AAE	PERICOM	获取价格	14-Bit Registered Buffer
PI74SSTVF16857AAEX	PERICOM	获取价格	D Flip-Flop, CMOS, PDSO48, 0.240 INCH, LEAD FREE, PLASTIC, TSSOP-48
PI74SSTVF16857AE	PERICOM	获取价格	暂无描述
PI74SSTVF16857AK	PERICOM	获取价格	14-Bit Registered Buffer

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