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NTB65N02R_05 PDF预览

NTB65N02R_05

更新时间: 2024-11-05 03:45:51
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 76K
描述
Power MOSFET 65 A, 24 V N-Channel TO-220, D2PAK

NTB65N02R_05 数据手册

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NTB65N02R, NTP65N02R  
Power MOSFET  
65 A, 24 V N−Channel  
TO−220, D2PAK  
Features  
http://onsemi.com  
Planar HD3e Process for Fast Switching Performance  
Low R  
to Minimize Conduction Loss  
DSon  
V
R
TYP  
I MAX  
D
(BR)DSS  
DS(on)  
Low C to Minimize Driver Loss  
iss  
24 V  
8.4 mW @ 10 V  
65 A  
Low Gate Charge  
Pb−Free Packages are Available*  
D
MAXIMUM RATINGS (T = 25°C Unless otherwise specified)  
J
G
Parameter  
Drain−to−Source Voltage  
Symbol Value Unit  
S
V
DSS  
25  
V
V
dc  
dc  
Gate−to−Source Voltage − Continuous  
Thermal Resistance − Junction−to−Case  
V
±20  
GS  
MARKING  
DIAGRAMS  
R
2.0  
°C/W  
q
JC  
Total Power Dissipation @ T = 25°C  
P
D
62.5  
W
C
Drain Current −  
Continuous @ T = 25°C, Chip  
Continuous @ T =25°C, Limited by Package  
Single Pulse (t = 10 ms)  
I
I
65  
58  
160  
A
A
A
C
D
C
D
4
TO−220AB  
CASE 221A  
STYLE 5  
I
p
DM  
Thermal Resistance −  
Junction−to−Ambient (Note 1)  
Total Power Dissipation @ T = 25°C  
Drain Current − Continuous @ T = 25°C  
P65N02RG  
AYWW  
R
P
I
67  
1.86  
10  
°C/W  
W
A
q
JA  
A
D
A
D
1
Thermal Resistance −  
Junction−to−Ambient (Note 2)  
Total Power Dissipation @ T = 25°C  
Drain Current − Continuous @ T = 25°C  
2
2
3
R
P
I
120  
1.04  
7.6  
°C/W  
W
A
q
JA  
A
D
A
D
2
D PAK  
Operating and Storage Temperature Range  
Single Pulse Drain−to−Source Avalanche  
T and  
−55 to  
150  
°C  
4
J
65N02RG  
AYWW  
CASE 418AA  
STYLE 2  
T
stg  
E
60  
mJ  
AS  
1
3
Energy − Starting T = 25°C  
J
(V = 50 V , V = 10 V , I = 11 A ,  
65N02R = Specific Device Code  
DD  
dc  
GS  
dc  
L
pk  
L = 1 mH, R = 25 W)  
A
Y
WW  
G
= Assembly Location  
= Year  
= Work Week  
G
Maximum Lead Temperature for Soldering  
Purposes, 1/8from Case for 10 Seconds  
T
L
260  
°C  
= Pb−Free Package  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
PIN ASSIGNMENT  
PIN  
FUNCTION  
2
1. When surface mounted to an FR4 board using 1 in. pad size, (Cu Area 1.127 in ).  
1
Gate  
2. When surface mounted to an FR4 board using minimum recommended pad  
2
size, (Cu Area 0.412 in ).  
2
3
Drain  
Source  
4
Drain  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
May, 2005 − Rev. 6  
NTB65N02R/D  
 

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