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MTD6N15T4 PDF预览

MTD6N15T4

更新时间: 2024-10-31 22:29:11
品牌 Logo 应用领域
安森美 - ONSEMI 晶体晶体管功率场效应晶体管
页数 文件大小 规格书
8页 92K
描述
Power Field Effect Transistor DPAK for Surface Mount

MTD6N15T4 技术参数

是否无铅: 含铅生命周期:End Of Life
包装说明:CASE 369C-01, DPAK-3针数:3
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8541.29.00.95风险等级:5.13
Is Samacsys:N外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:150 V
最大漏极电流 (Abs) (ID):6 A最大漏极电流 (ID):6 A
最大漏源导通电阻:0.3 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PSSO-G2JESD-609代码:e0
湿度敏感等级:1元件数量:1
端子数量:2工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):20 W最大脉冲漏极电流 (IDM):20 A
认证状态:Not Qualified子类别:FET General Purpose Power
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子位置:SINGLE
处于峰值回流温度下的最长时间:30晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

MTD6N15T4 数据手册

 浏览型号MTD6N15T4的Datasheet PDF文件第2页浏览型号MTD6N15T4的Datasheet PDF文件第3页浏览型号MTD6N15T4的Datasheet PDF文件第4页浏览型号MTD6N15T4的Datasheet PDF文件第5页浏览型号MTD6N15T4的Datasheet PDF文件第6页浏览型号MTD6N15T4的Datasheet PDF文件第7页 
MTD6N15  
Power Field Effect  
Transistor DPAK  
for Surface Mount  
N−Channel Enhancement−Mode Silicon  
Gate  
http://onsemi.com  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(on)  
This TMOS Power FET is designed for high speed, low loss power  
switching applications such as switching regulators, converters,  
solenoid and relay drivers.  
150 V  
0.3 W  
6.0 A  
N−CHANNEL  
Silicon Gate for Fast Switching Speeds  
D
Low R  
— 0.3 Max  
DS(on)  
Rugged — SOA is Power Dissipation Limited  
Source−to−Drain Diode Characterized for Use With  
Inductive Loads  
G
Low Drive Requirement — V  
= 4.0 V Max  
GS(th)  
Surface Mount Package on 16 mm Tape  
S
4
4
MAXIMUM RATINGS  
Rating  
Drain−Source Voltage  
Symbol  
Value  
150  
Unit  
Vdc  
Vdc  
2
1
V
DSS  
DGR  
3
1
2
Drain−Gate Voltage (R = 1.0 M)  
V
V
150  
GS  
3
CASE 369C  
DPAK  
(Surface Mount)  
STYLE 2  
CASE 369D  
DPAK  
(Straight Lead)  
STYLE 2  
Gate−Source Voltage — Continuous  
V
± 20  
± 40  
Vdc  
Vpk  
GS  
GSM  
Gate−Source Voltage — Non−Repetitive  
(t 50 µs)  
p
Drain Current — Continuous  
Drain Current — Pulsed  
I
6.0  
20  
Adc  
D
MARKING DIAGRAM  
& PIN ASSIGNMENTS  
I
DM  
Total Power Dissipation @ T = 25°C  
Derate above 25°C  
P
D
P
D
P
D
20  
0.16  
Watts  
W/°C  
C
4 Drain  
4 Drain  
Total Power Dissipation @ T = 25°C  
1.25  
0.01  
Watts  
W/°C  
A
Derate above 25°C (Note 1)  
Total Power Dissipation @ T = 25°C (1)  
1.75  
Watts  
A
Derate above 25°C (Note 2)  
0.014  
W/°C  
1
Gate  
3
2
Source  
1
3
Operating and Storage Junction Temper-  
ature Range  
T , T  
65 to  
+150  
°C  
J
stg  
Drain  
Gate  
Source  
6N15  
Y
= Device Code  
= Year  
= Work Week  
2
THERMAL CHARACTERISTICS  
Characteristic  
Drain  
WW  
Symbol  
Value  
Unit  
Thermal Resistance  
− Junction to Case  
− Junction to Ambient (Note 1)  
− Junction to Ambient (Note 2)  
ORDERING INFORMATION  
R
R
R
6.25  
100  
71.4  
θ
JC  
JA  
JA  
°C/W  
Device  
Package  
Shipping  
θ
θ
MTD6N15  
DPAK  
75 Units/Rail  
1. When surface mounted to an FR4 board using the minimum recommended  
pad size.  
DPAK  
Straight Lead  
MTD6N15−1  
75 Units/Rail  
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.  
MTD6N15T4  
DPAK  
2500 Tape & Reel  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
March, 2004 − Rev. 2  
MTD6N15/D  
 

MTD6N15T4 替代型号

型号 品牌 替代类型 描述 数据表
MTD6N15T4G ONSEMI

类似代替

N−Channel Enhancement−Mode Silicon Gate
MTD6N15 MOTOROLA

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