Datasheet > MPC9331AC

MPC9331AC

更新时间： 2023-01-02 14:58:57

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
12页	321K
描述
9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FREE, LQFP-32

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MPC9331AC 数据手册

MPC9331

Rev. 7, 1/2005

Freescale Semiconductor

Technical Data

3.3 V 1:6 LVCMOS PLL Clock

Generator

MPC9331

The MPC9331 is a 3.3 V compatible, 1:6 PLL based clock generator targeted

for high performance low-skew clock distribution in mid-range to high-performance

telecom, networking, and computing applications. With output frequencies up to

240 MHz and output skews less than 150 ps, the device meets the needs of most

the demanding clock applications. The MPC9331 is specified for the temperature

range of 0°C to +70°C.

LOW VOLTAGE

3.3 V LVCMOS 1:6

CLOCK GENERATOR

Features

•

1:6 PLL based low-voltage clock generator

3.3 V power supply

Generates clock signals up to 240 MHz

Maximum output skew of 150 ps

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

Differential LVPECL reference clock input

Alternative LVCMOS PLL reference clock input

Internal and external PLL feedback

Supports zero-delay operation in external feedback mode

PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3

or x/4

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

•

Synchronous output clock stop in logic low eliminates output runt pulses

Power_down feature reduces output clock frequency

Drives up to 12 clock lines

32-lead LQFP packaging

32-lead Pb-free Package Available

Ambient temperature range 0°C to +70°C

Internal Power-Up Reset

Pin and function compatible to the MPC931

Functional Description

The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback

input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback

path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback

configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the

MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration

(divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a

division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC

pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.

The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN

control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is

routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency

specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the

OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to

missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling

the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop

synchronously in logic low state, without the potential generation of runt pulses.

The MPC9331 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω

transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the

devices an effective fanout of 1:12. The device is packaged in a 7x7 mm²32-lead LQFP package.

12 3 4 5 6 7...12

中文翻译

下载PDF

与MPC9331AC相关器件

型号	品牌	获取价格	描述	数据表
MPC9331ACR2	NXP	获取价格	9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9331FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC9331FA	NXP	获取价格	9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9331FAR2	NXP	获取价格	IC,1:6 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9331FAR2	IDT	获取价格	PLL Based Clock Driver, 9331 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9350	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC9350AC	NXP	获取价格	IC,1:9 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9350ACR2	NXP	获取价格	IC,1:9 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9350D	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC9350FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,

与MPC9331AC相关文章

LTM4644/LTM4644-1：创新的四输出同步降压微模块调节器
2024-07-02

3
2N3500：一款多用途NPN硅晶体管的全面解析
2024-07-02

6
最详细资料解析：BA5917AFP参数说明、引脚说明
2024-07-02

10
MAX232IDR数据手册：产品特性、电气参数、替代型号推荐
2024-07-02

4

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9331AC

MPC9331AC 数据手册

与MPC9331AC相关器件

与MPC9331AC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9331AC

MPC9331AC 数据手册

与MPC9331AC相关器件

与MPC9331AC相关文章

您还可以找

您在本页遇到什么问题？