5秒后页面跳转
CY62256VNLL-70ZRIT PDF预览

CY62256VNLL-70ZRIT

更新时间: 2024-11-25 13:02:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 410K
描述
暂无描述

CY62256VNLL-70ZRIT 数据手册

 浏览型号CY62256VNLL-70ZRIT的Datasheet PDF文件第2页浏览型号CY62256VNLL-70ZRIT的Datasheet PDF文件第3页浏览型号CY62256VNLL-70ZRIT的Datasheet PDF文件第4页浏览型号CY62256VNLL-70ZRIT的Datasheet PDF文件第5页浏览型号CY62256VNLL-70ZRIT的Datasheet PDF文件第6页浏览型号CY62256VNLL-70ZRIT的Datasheet PDF文件第7页 
CY62256VN  
256K (32K x 8) Static RAM  
Features  
Functional Description  
Temperature Ranges  
The CY62256VN[1] family is composed of two high performance  
CMOS static RAM’s organized as 32K words by 8 bits. Easy  
memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and tristate drivers.  
These devices have an automatic power down feature, reducing  
the power consumption by over 99% when deselected.  
Commercial: 0°C to 70°C  
Industrial: –40°C to 85°C  
Automotive-A: –40°C to 85°C  
Automotive-E: –40°C to 125°C  
Speed: 70 ns  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location addressed  
by the address present on the address pins (A0 through A14).  
Reading the device is accomplished by selecting the device and  
enabling the outputs, CE and OE active LOW, while WE remains  
inactive or HIGH. Under these conditions, the contents of the  
location addressed by the information on address pins are  
present on the eight data input/output pins.  
Low Voltage Range: 2.7V to 3.6V  
Low Active Power and Standby Power  
Easy Memory Expansion with CE and OE Features  
TTL Compatible Inputs and Outputs  
Automatic Power Down when Deselected  
CMOS for Optimum Speed and Power  
The input/output pins remain in a high impedance state unless  
the chip is selected, outputs are enabled, and write enable (WE)  
is HIGH.  
Available in Standard Pb-free and non Pb-free 28-Pin (300-mil)  
Narrow SOIC, 28-Pin TSOP-I, and 28-Pin Reverse TSOP-I  
Packages  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
A
A
10  
9
8
A
7
6
5
A
32K x 8  
ARRAY  
A
A
A
A
4
3
2
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
.
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06512 Rev. *B  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised September 25, 2009  
[+] Feedback  

与CY62256VNLL-70ZRIT相关器件

型号 品牌 获取价格 描述 数据表
CY62256VNLL-70ZRXE CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62256VNLL-70ZRXI CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62256VNLL-70ZXA CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62256VNLL-70ZXC CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62256VNLL-70ZXE CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62256VNLL-70ZXET CYPRESS

获取价格

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28
CY62256VNLL-70ZXI CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62512VL-55ZC CYPRESS

获取价格

Standard SRAM, 64KX8, 55ns, CMOS, PDSO32
CY62512VLL-55ZI CYPRESS

获取价格

Standard SRAM, 64KX8, 55ns, CMOS, PDSO32
CY62512VLL-70ZC CYPRESS

获取价格

Standard SRAM, 64KX16, 70ns, CMOS, PDSO32, TSOP1-32