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CY6264_06

更新时间： 2024-11-25 04:38:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 270K
描述
8K x 8 Static RAM

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中文翻译

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CY6264_06 数据手册

 浏览型号CY6264_06的Datasheet PDF文件第2页浏览型号CY6264_06的Datasheet PDF文件第3页浏览型号CY6264_06的Datasheet PDF文件第4页浏览型号CY6264_06的Datasheet PDF文件第5页浏览型号CY6264_06的Datasheet PDF文件第6页浏览型号CY6264_06的Datasheet PDF文件第7页 
CY6264  
8K x 8 Static RAM  
Features  
Functional Description  
• Temperature Ranges  
The CY6264 is a high-performance CMOS static RAM  
organized as 8192 words by 8 bits. Easy memory expansion  
is provided by an active LOW chip enable (CE1), an active  
HIGH chip enable (CE2), and active LOW output enable (OE)  
and three-state drivers. Both devices have an automatic  
power-down feature (CE1), reducing the power consumption  
by over 70% when deselected. The CY6264 is packaged in a  
450-mil (300-mil body) SOIC.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
• High Speed  
— 55 ns  
• CMOS for optimum speed/power  
• Easy memory expansion with CE1, CE2 and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE1 and WE  
inputs are both LOW and CE2 is HIGH, data on the eight data  
input/output pins (I/O0 through I/O7) is written into the memory  
location addressed by the address present on the address  
pins (A0 through A12). Reading the device is accomplished by  
selecting the device and enabling the outputs, CE1 and OE  
active LOW, CE2 active HIGH, while WE remains inactive or  
HIGH. Under these conditions, the contents of the location  
addressed by the information on address pins is present on  
the eight data input/output pins.  
• Available in Pb-free and non Pb-free 28-lead SNC  
package  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH. A die coat is used to ensure alpha immunity.  
Logic Block Diagram  
Pin Configuration  
SOIC  
Top View  
NC  
V
CC  
WE  
CE  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A
4
A
5
A
6
2
2
3
A
3
A
2
A
1
4
I/O  
I/O  
0
A
7
5
INPUT BUFFER  
A
8
6
1
A
OE  
A
0
CE  
9
7
A
10  
11  
12  
8
A
A
1
7
6
5
4
3
9
A
1
I/O  
I/O  
2
I/O  
I/O  
I/O  
I/O  
I/O  
10  
11  
12  
13  
14  
A
2
I/O  
0
I/O  
1
I/O  
2
A
3
3
A
4
8K x 8  
GND  
ARRAY  
A
5
I/O  
I/O  
I/O  
I/O  
4
5
6
7
A
6
A
7
A
8
POWER  
DOWN  
CE  
1
COLUMN DECODER  
CE  
2
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 001-02367 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 8, 2006  
[+] Feedback  
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