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CY62256VNLL-70ZXI PDF预览

CY62256VNLL-70ZXI

更新时间: 2024-11-09 04:38:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 645K
描述
256K (32K x 8) Static RAM

CY62256VNLL-70ZXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP1, TSSOP28,.53,22针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41Factory Lead Time:1 week
风险等级:7.79最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G28
JESD-609代码:e4长度:11.8 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP28,.53,22
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3/3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.000006 A
最小待机电流:1.4 V子类别:SRAMs
最大压摆率:0.03 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.55 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:8 mmBase Number Matches:1

CY62256VNLL-70ZXI 数据手册

 浏览型号CY62256VNLL-70ZXI的Datasheet PDF文件第2页浏览型号CY62256VNLL-70ZXI的Datasheet PDF文件第3页浏览型号CY62256VNLL-70ZXI的Datasheet PDF文件第4页浏览型号CY62256VNLL-70ZXI的Datasheet PDF文件第5页浏览型号CY62256VNLL-70ZXI的Datasheet PDF文件第6页浏览型号CY62256VNLL-70ZXI的Datasheet PDF文件第7页 
CY62256VN  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62256VN family is composed of two high-performance  
CMOS static RAM’s organized as 32K words by 8 bits. Easy  
memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and tri-state drivers.  
These devices have an automatic power-down feature,  
reducing the power consumption by over 99% when  
deselected.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• Speed: 70 ns  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
• Low voltage range: 2.7V–3.6V  
• Low active power and standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in standard Pb-free and non Pb-free 28-lead  
(300-mil) narrow SOIC, 28-lead TSOP-I and 28-lead  
Reverse TSOP-I packages  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
A
A
10  
9
8
A
7
6
5
A
32K x 8  
ARRAY  
A
A
A
A
4
3
2
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06512 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 3, 2006  
[+] Feedback  

CY62256VNLL-70ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62256VNLL-70ZXA CYPRESS

完全替代

256K (32K x 8) Static RAM
CY62256VNLL-70ZXC CYPRESS

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256K (32K x 8) Static RAM

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