Datasheet > CY62167DV30LL-55ZXIT

CY62167DV30LL-55ZXIT

更新时间： 2024-11-06 14:56:11

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
18页	327K
描述
Asynchronous SRAM

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CY62167DV30LL-55ZXIT 数据手册

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CY62167DV30 MoBL^®

16-Mbit (1 M × 16) Static RAM

16-Mbit (1

M × 16) Static RAM

automatic power-down feature that significantly reduces power

consumption by 99% when addresses are not toggling. The

device can also be put into standby mode when deselected (CE₁

HIGH or CE₂LOW or both BHE and BLE are HIGH). The

Features

■ Thin small outline package (TSOP-I) configurable as

1 M × 16 or as 2 M × 8 SRAM

input/output pins (I/O₀through I/O₁₅

) are placed in a

■ Wide voltage range: 2.2 V–3.6 V

high-impedance state when: deselected (CE₁HIGH or CE₂

LOW), outputs are disabled (OE HIGH), both Byte High Enable

and Byte Low Enable are disabled (BHE, BLE HIGH), or during

a Write operation (CE₁LOW, CE₂HIGH and WE LOW).

■ Ultra-low active power:

Typical active current: 2 mA at f = 1 MHz

■ Ultra-low standby power

Writing to the device is accomplished by taking Chip Enables

(CE₁LOW and CE₂HIGH) and Write Enable (WE) input LOW. If

Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀

through I/O₇), is written into the location specified on the address

pins (A₀through A₁₉). If Byte High Enable (BHE) is LOW, then

data from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₉).

■ Easy memory expansion with CE₁, CE₂and OE features

■ Automatic power-down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed / power

■ Available in Pb-free and non Pb-free 48-ball very fine-pitch ball

grid array (VFBGA) and 48-pin TSOP I package

Reading from the device is accomplished by taking Chip Enables

(CE₁LOW and CE₂HIGH) and Output Enable (OE) LOW while

forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)

is LOW, then data from the memory location specified by the

address pins appear on I/O₀to I/O₇. If Byte High Enable (BHE)

is LOW, then data from memory appear on I/O₈to I/O₁₅. See the

truth table at the back of this data sheet for a complete

description of Read and Write modes.

Functional Description

The CY62167DV30 is a high-performance CMOS static RAM

organized as 1M words by 16-bits. This device features

advanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life (MoBL^) in portable

applications such as cellular telephones. The device also has an

For a complete list of related documentation, click here.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

1M × 16 / 2M x 8

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BYTE

BHE

CE₂

CE₁

BLE

Power-Down

Circuit

CE₂

CE₁

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05328 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 19, 2014

12 3 4 5 6 7...18

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与CY62167DV30LL-55ZXIT相关器件

型号	品牌	获取价格	描述	数据表
CY62167DV30LL-70BVI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167DV30LL-70BVI	INFINEON	获取价格	Asynchronous SRAM
CY62167DV30LL-70BVIT	INFINEON	获取价格	Asynchronous SRAM
CY62167DV30LL-70BVXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167DV30LL-70ZI	ROCHESTER	获取价格	1MX16 STANDARD SRAM, 70ns, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, TSOP1-48
CY62167DV30LL-70ZI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167DV30LL-70ZIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 70ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, TSOP1-48
CY62167DV30LL-70ZXI	ROCHESTER	获取价格	1MX16 STANDARD SRAM, 70ns, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-48
CY62167DV30LL-70ZXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 70ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-48
CY62167E	CYPRESS	获取价格	16-Mbit (1M x 16 / 2M x 8) Static RAM

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